Datasheet

STM8L052C6 Memory and register map
Doc ID 022924 Rev 2 27/52
5 Memory and register map
5.1 Memory mapping
The memory map is shown in Figure 4.
Figure 4. Memory map
1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end
address.
2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware
registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.
GPIO and peripheral registers
0x00 0000
Reserved
Medium density
(32 Kbytes)
Reset and interrupt vectors
0x00 1000
0x00 10FF
RAM
0x00 07FF
(2 Kbytes)
(1)
(513 bytes)
(1)
0x00 1100
Data EEPROM
0x00 4800
0x00 48FF
0x00 4900
0x00 7FFF
0x00 8000
0x00 FFFF
0x00 0800
0x00 0FFF
0x00 47FF
0x00 7EFF
0x00 8080
0x00 807F
0x00 7F00
Reserved
including
Stack
(256 bytes)
Option bytes
0x00 4FFF
0x00 5000
0x00 57FF
0x00 5800
Reserved
0x00 5FFF
Boot ROM
0x00 6000
0x00 67FF
(2 Kbytes)
0x00 6800
Reserved
CPU/SWIM/Debug/ITC
Registers
0x00 5000
GPIO Ports
0x00 5050
Flash
0x00 50C0
ITC-EXTI
0x00 50D3
RST
0x00 50E0
CLK
0x00 50F3
WWDG
0x00 5210
IWDG
0x00 5230
BEEP
0x00 5250
RTC
0x00 5280
SPI1
0x00 52B0
I2C1
0x00 52E0
USART1
TIM2
TIM3
TIM1
TIM4
IRTIM
ADC1
0x00 5070
DMA1
SYSCFG
LCD
RI
0x00 509E
0x00 50A0
0x00 50B0
0x00 5140
0x00 5200
0x00 52FF
0x00 5340
0x00 5380
0x00 5400
0x00 5430
0x00 5440
Flash program memory
WFE
0x00 50A6
0x00 50B2
PWR
Reserved
Reserved
Reserved