Datasheet

Memory and register map STM8L051F3
24/46 Doc ID 022985 Rev 1
5 Memory and register map
5.1 Memory mapping
The memory map is shown in Figure 4.
Figure 4. Memory map
1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end
address.
2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware
registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.
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