Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 20 8-Bit 16 MHz I/O number 18

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice. For further information contact your local STMicroelectronics sales office.

April 2012 Doc ID 022985 Rev 1 1/46

STM8L051F3

Value line, 8-bit ultralow power MCU, 8-KB Flash,

256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC

Data brief  preliminary data

Features

■ Operating conditions

– Operating power supply: 1.8 V to 3.6 V

Temperature range: 40 °C to 85 °C

■ Low power features

– 5 low power modes: Wait, Low power run,

Low power wait, Active-halt with RTC, Halt

– Ultralow leakage per I/0: 50 nA

– Fast wakeup from Halt: 5 µs

■ Advanced STM8 core

– Harvard architecture and 3-stage pipeline

– Max freq: 16 MHz, 16 CISC MIPS peak

– Up to 40 external interrupt sources

■ Reset and supply management

– Low power, ultrasafe BOR reset with 5

selectable thresholds

– Ultra low power POR/PDR

– Programmable voltage detector (PVD)

■ Clock management

– 32 kHz and 1 to 16 MHz crystal oscillators

– Internal 16 MHz factory-trimmed RC

– Internal 38 kHz low consumption RC

– Clock security system

■ Low power RTC

– BCD calendar with alarm interrupt

– Digital calibration with +/- 0.5 ppm accuracy

– LSE security system

– Auto-wakeup from Halt w/ periodic interrupt

■ Memories

– 8 Kbytes of Flash program memory and

256 bytes of data EEPROM with ECC

– Flexible write and read protection modes

– 1 Kbyte of RAM

■ DMA

– 4 channels supporting ADC, SPI, I2C,

USART, timers

– 1 channel for memory-to-memory

■ 12-bit ADC up to 1 Msps/28 channels

– Internal reference voltage

■ Timers

– Two 16-bit timers with 2 channels (used as

IC, OC, PWM), quadrature encoder

– One 8-bit timer with 7-bit prescaler

–

2 watchdogs: 1 Window, 1 Independent

– Beeper timer with 1, 2 or 4 kHz frequencies

■ Communication interfaces

– Synchronous serial interface (SPI)

–Fast I

C 400 kHz SMBus and PMBus

–USART

■ Up to 18 I/Os, all mappable on interrupt vectors

■ Development support

– Fast on-chip programming and non-

intrusive debugging with SWIM

– Bootloader using USART

Table 1. Device summary

Reference Part number

STM8L051xx STM8L051F3

TSSOP20

www.st.com

Summary of content (46 pages)

PAGE 1
STM8L051F3 Value line, 8-bit ultralow power MCU, 8-KB Flash, 256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC Data brief  preliminary data Features ■ Operating conditions – Operating power supply: 1.8 V to 3.
PAGE 2
Contents STM8L051F3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional overview . . .
PAGE 3
STM8L051F3 3.15 4 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 5 Contents System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
List of tables STM8L051F3 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. 4/46 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Low density value line STM8L05xxx low power device features and peripheral counts. . . . 8 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
STM8L051F3 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Low density value line STM8L05xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . 10 Low density value line STM8L05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STM8L051Fx 20-pin TSSOP20 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory map . . . . . . . . . . . . . . . . . . . . .
PAGE 6
Introduction 1 STM8L051F3 Introduction This document describes the features, pinout, mechanical data and ordering information for the low density value line STM8L151F3 microcontroller with 8-Kbyte Flash memory density. For more details on the whole STMicroelectronics ultra low power family please refer to Section 2.2: Ultra low power continuum. For detailed information on device operation and registers, refer to the reference manual (RM0031).
PAGE 7
STM8L051F3 2 Description Description The low density value line STM8L05xxx devices are members of the STM8L ultra low power 8-bit family. The STM8L ultra low power family features an enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.
PAGE 8
Description 2.1 STM8L051F3 Device overview Table 2.
PAGE 9
STM8L051F3 2.2 Description Ultra low power continuum The ultra low power value line STM8L05xxx are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers ultra low power strategy which also includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features. They are all based on STMicroelectronics 0.
PAGE 10
Functional overview STM8L051F3 3 Functional overview Figure 1. Low density value line STM8L05xxx device block diagram /3#?). /3#?/54 -(Z INTERNAL 2# /3# ?). /3# ?/54 6$$ -(Z OSCILLATOR K(Z OSCILLATOR 6$$ #LOCK CONTROLLER AND #33 6/,4 2%' #LOCKS TO CORE AND PERIPHERALS K(Z INTERNAL 2# )NTERRUPT CONTROLLER 2%3%4 CHANNELS BIT 4IMER CHANNELS BIT 4IMER 6 $$! 6 33! !$# ?).
PAGE 11
STM8L051F3 3.1 Functional overview Low power modes The low density value line STM8L05xxx devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Wait mode: The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode). ● Low power run mode: The CPU and the selected peripherals are running.
PAGE 12
Functional overview STM8L051F3 3.2 Central processing unit STM8 3.2.1 Advanced STM8 Core The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions.
PAGE 13
STM8L051F3 Functional overview 3.3 Reset and supply management 3.3.1 Power supply scheme The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows: 3.3.2 ● VSS1 ; VDD1 = 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator. Provided externally through VDD1 pins, the corresponding ground pin is VSS1. ● VSSA; VDDA = 1.8 to 3.6 V: external power supplies for analog peripherals.
PAGE 14
Functional overview 3.4 STM8L051F3 Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features 14/46 ● Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
PAGE 15
STM8L051F3 Functional overview Figure 2. Low density value line STM8L05xxx clock tree diagram 37)-; = /3#?/54 /3#?). (3% /3# -(Z (3% (3) (3) 2# -(Z ,3) 393#,+ PRESCALER 393#,+ TO CORE AND MEMORY 0#,+ TO PERIPHERALS 0ERIPHERAL #LOCK ENABLE BITS ,3% ,3% "%%0#,+ TO "%%0 )7$'#,+ TO )7$' #,+"%%03%,; = ,3) ,3) 2# K(Z 24#3%,; = /3# ?/54 /3# ?).
PAGE 16
Functional overview 3.5 STM8L051F3 Low power real-time clock The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter. Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically. It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability. 3.6 ● Periodic wakeup time using the 32.
PAGE 17
STM8L051F3 3.9 Functional overview System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped. The highly flexible routing interface controls the routing of internal analog signals to ADC1 and the internal reference voltage VREFINT. 3.
PAGE 18
Functional overview 3.11.1 STM8L051F3 Window watchdog timer The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.11.2 Independent watchdog timer The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures.
PAGE 19
STM8L051F3 3.13.3 Functional overview USART The USART interface (USART1) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. ● 1 Mbit/s full duplex SCI ● SPI1 emulation ● High precision baud rate generator ● Smartcard emulation ● IrDA SIR encoder decoder ● Single wire half duplex mode Note: USART1 can be served by the DMA1 Controller. 3.
PAGE 20
Functional overview STM8L051F3 Bootloader The low density value line STM8L05xxx ultra low power devices feature a built-in bootloader (see UM0560: STM8 bootloader user manual). The bootloader is used to download application software into the device memories, including RAM, program and data memory, using standard serial interfaces. It is a complementary solution to programming via the SWIM debugging interface.
PAGE 21
STM8L051F3 4 Pin description Pin description Figure 3. STM8L051Fx 20-pin TSSOP20 package pinout 0# 0# 0! .234 0! 0! 0! 633 633! 62%& 6$$ 6$$! 62%& 0$ 0" 0# 0# 0# 0" 0" 0" 0" 0" 0" 0" -3 6 Low density value line STM8L05xxx pin description 4 NRST/PA1(1) (2)/ I/O X HS Main function (after reset) PP OD Output Ext.
PAGE 22
Pin description Low density value line STM8L05xxx pin description (continued) I/O X 18 PC0/I2C_SDA I/O X 19 PC1/I2C_SCL X HS X I/O X X T(4) X (3) T Main function (after reset) X PP Ext. interrupt 17 PB7/SPI1_MISO/ADC1_IN11 Output wpu floating Pin name Type TSSOP20 Input OD pin n° High sink/source Table 4.
PAGE 23
STM8L051F3 4.1 Pin description System configuration options As shown in Table 4: Low density value line STM8L05xxx pin description, some alternate functions can be remapped on different I/O ports by programming one of the two remapping registers described in the “ Routing interface (RI) and system configuration controller” section in the STM8L15xx and STM8L16xx reference manual (RM0031).
PAGE 24
Memory and register map STM8L051F3 5 Memory and register map 5.1 Memory mapping The memory map is shown in Figure 4. Figure 4.
PAGE 25
STM8L051F3 Table 5. Memory and register map Flash and RAM boundary addresses Memory area Size Start address End address RAM 1 Kbyte 0x00 0000 0x00 03FF Flash program memory 8 Kbytes 0x00 8000 0x00 9FFF 5.2 Register map Table 6.
PAGE 26
Memory and register map Table 7.
PAGE 27
STM8L051F3 Table 7.
PAGE 28
Memory and register map Table 7.
PAGE 29
STM8L051F3 Table 7.
PAGE 30
Memory and register map Table 7.
PAGE 31
STM8L051F3 Table 7.
PAGE 32
Memory and register map Table 7.
PAGE 33
STM8L051F3 Table 7.
PAGE 34
Memory and register map Table 7.
PAGE 35
STM8L051F3 Table 7.
PAGE 36
Memory and register map Table 8.
PAGE 37
STM8L051F3 Table 8. Memory and register map CPU/SWIM/debug module/interrupt controller registers (continued) Register label Register name Reset status DM_CR2 DM Debug module control register 2 0x00 DM_CSR1 DM Debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF Address Block 0x00 7F97 0x00 7F98 DM 0x00 7F9B to 0x00 7F9F Reserved area (5 bytes) 1.
PAGE 38
Interrupt vector mapping STM8L051F3 6 Interrupt vector mapping Table 9. Interrupt mapping IRQ No.
PAGE 39
STM8L051F3 Table 9. Interrupt vector mapping Interrupt mapping (continued) Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode)(1) TIM2 Capture/Compare interrupt - - Yes Yes 0x00 8058 TIM3 TIM3 Update /Overflow/Trigger/Break interrupt - - Yes Yes 0x00 805C 22 TIM3 TIM3 Capture/Compare interrupt - - Yes Yes 0x00 8060 23 RI RI trigger interrupt - - Yes - 0x00 8064 IRQ No.
PAGE 40
Package characteristics STM8L051F3 7 Package characteristics 7.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
PAGE 41
STM8L051F3 Package characteristics 7.2 Package mechanical data 7.2.1 20-lead thin shrink small package (TSSOP20) Figure 5. TSSOP20 20-lead thin shrink small package Figure 6. outline TSSOP20 recommended footprint D 20 11 c E1 1 E 10 α L A1 A A2 L1 CP b e TSSOP20-M BJ 1. Drawing is not to scale 2. Dimensions are in millimeters Table 10. TSSOP20 20-lead thin shrink small package, mechanical data Dim. inches(1) mm Min Typ A Max Min Typ 1.2 A1 0.05 A2 0.8 b Max 0.
PAGE 42
Package characteristics STM8L051F3 7.2.2 32-pin Low profile quad flat package (LQFP32) Figure 7. LQFP32 32-pin low profile quad flat package outline ccc C D D1 D3 24 A A2 17 16 25 L1 b E3 32 E1 E 9 Pin 1 identification L A1 1 K c 8 5V_ME Table 11. LQFP32 32-pin low profile quad flat package, mechanical data Dim. millimeters Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 D 8.800 D1 6.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.
PAGE 43
STM8L051F3 Figure 8. Package characteristics LQFP32 recommended footprint 9.40 7.70 0.54 9.40 0.80 5V_FP 1.
PAGE 44
Device ordering information 8 STM8L051F3 Device ordering information Figure 9. Low density value line STM8L05xxx ordering information scheme Example: STM8 L 051 F 3 P 6 Product class STM8 microcontroller Family type L = Low power Sub-family type 051 = Ultra low power Pin count F = 20 pins Program memory size 3 = 8 Kbytes Package P = TSSOP Temperature range 6 = – 40 to 85 °C For a list of available options (e.g.
PAGE 45
STM8L051F3 9 Revision history Revision history Table 12. Document revision history Date Revision 23-Apr-2012 1 Changes Initial release.
PAGE 46
STM8L051F3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.