Datasheet

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics
Doc ID 14395 Rev 9 79/110
Figure 39. SPI timing diagram in slave mode and with CPHA = 0
1. Measurement points are at CMOS levels: 0.3 V
DD
and 0.7 V
DD
.
Figure 40. SPI timing diagram in slave mode and with CPHA = 1
1. Measurement points are at CMOS levels: 0.3 V
DD
and 0.7 V
DD
.
ai14134
SCK Input
CPHA= 0
MOSI
INPUT
MISO
OUT P UT
CPHA= 0
MS B O UT
MSB IN
BI T6 O U T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
t
SU(NSS)
t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUT P UT
CPHA=1
MS B O UT
MSB IN
BI T6 O U T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
t
SU(NSS)
t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
NSS input