Datasheet

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx
78/110 Doc ID 14395 Rev 9
10.3.9
SPI interface
Unless otherwise specified, the parameters given in Tabl e 43 are derived from tests
performed under ambient temperature, f
MASTER
frequency, and V
DD
supply voltage
conditions. t
MASTER
= 1/f
MASTER
.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 43. SPI characteristics
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master mode 0 10
MHz
Slave mode
V
DD
< 4.5 V 0 6
(1)
V
DD
= 4.5 V to 5.5 V 0 8
(1)
t
r(SCK)
t
f(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF — 25
(2)
ns
t
su(NSS)
(3)
NSS setup time Slave mode 4 * t
MASTER
—
t
h(NSS)
(3)
NSS hold time Slave mode 70 —
t
w(SCKH)
(3)
t
w(SCKL)
(3)
SCK high and low time Master mode t
SCK
/2 - 15 t
SCK
/2 + 15
t
w(SCKH)
(3)
t
w(SCKL)
(3)
t
su(MI)
(3)
t
su(SI)
(3)
Data input setup time
Master mode 5 —
Slave mode 5 —
t
h(MI)
(3)
t
h(SI)
(3)
Data input hold time
Master mode 7 —
Slave mode 10 —
t
a(SO)
(3)(4)
Data output access time Slave mode — 3* t
MASTER
t
dis(SO)
(3)(5)
Data output disable time Slave mode 25
t
v(SO)
(3)
Data output valid time
Slave mode
(after enable edge)
V
DD
< 4.5 V — 75
V
DD
= 4.5 V to 5.5 V — 53
t
v(MO)
(3)
Data output valid time Master mode (after enable edge) — 30
t
h(SO)
(3)
Data output hold time
Slave mode (after enable edge) 31 —
t
h(MO)
(3)
Master mode (after enable edge) 12 —
1. f
SCK
< f
MASTER
/2.
2. The pad has to be configured accordingly (fast mode).
3. Values based on design simulation and/or characterization results, and not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.