Datasheet

STM8AF52/62xx, STM8AF51/61xx Option bytes
Doc ID 14395 Rev 9 51/110
9 Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Each option
byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented
one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in
Table 20: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be changed in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 20. Option bytes
Addr.
Option
name
Option
byte
no.
Option bits Factory
default
setting
76543 2 1 0
0x00
4800
Read-out
protection
(ROP)
OPT0 ROP[7:0] 0x00
0x00
4801
User boot
code
(UBC)
OPT1 UBC[7:0] 0x00
0x00
4802
NOPT1 NUBC[7:0] 0xFF
0x00
4803
Alternate
function
remapping
(AFR)
OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00
0x00
4804
NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF
0x00
4805
Watchdog
option
OPT3 Reserved
LSI_
EN
IWDG
_HW
WWD
G _HW
WWDG
_HALT
0x00
0x00
4806
NOPT3 Reserved
NLSI_
EN
NIWD
G_HW
NWWD
G_HW
NWWG
_HALT
0xFF
0x00
4807
Clock
option
OPT4 Reserved
EXT
CLK
CKAW
USEL
PRSC1 PRSC0 0x00
0x00
4808
NOPT4 Reserved
NEXT
CLK
NCKAW
USEL
NPRSC1
NPRSC
0
0xFF
0x00
4809
HSE clock
startup
OPT5 HSECNT[7:0] 0x00
0x00
480A
NOPT5 NHSECNT[7:0] 0xFF