Datasheet

Interrupt table STM8AF52/62xx, STM8AF51/61xx
50/110 Doc ID 14395 Rev 9
8 Interrupt table
Table 19. STM8A interrupt table
(1)
Priority Source block Description
Interrupt vector
address
Wakeup
from Halt
Comments
— Reset Reset 0x00 6000 Yes Reset vector in ROM
— TRAP SW interrupt 0x00 8004 — —
0 TLI External top level interrupt 0x00 8008 — —
1 AWU Auto-wakeup from Halt 0x00 800C Yes —
2
Clock
controller
Main clock controller 0x00 8010 — —
3 MISC External interrupt E0 0x00 8014 Yes Port A interrupts
4 MISC External interrupt E1 0x00 8018 Yes Port B interrupts
5 MISC External interrupt E2 0x00 801C Yes Port C interrupts
6 MISC External interrupt E3 0x00 8020 Yes Port D interrupts
7 MISC External interrupt E4 0x00 8024 Yes Port E interrupts
8 CAN CAN interrupt Rx 0x00 8028 Yes —
9 CAN CAN interrupt TX/ER/SC 0x00 802C — —
10 SPI End of transfer 0x00 8030 Yes —
11 Timer 1
Update/overflow/
trigger/break
0x00 8034 — —
12 Timer 1 Capture/compare 0x00 8038 — —
13 Timer 2 Update/overflow 0x00 803C — —
14 Timer 2 Capture/compare 0x00 8040 — —
15 Timer 3 Update/overflow 0x00 8044 — —
16 Timer 3 Capture/compare 0x00 8048 — —
17 USART Tx complete 0x00 804C — —
18 USART Receive data full reg. 0x00 8050 — —
19 I
2
C I
2
C interrupts 0x00 8054 Yes —
20 LINUART Tx complete/error 0x00 8058 — —
21 LINUART Receive data full reg. 0x00 805C — —
22 ADC End of conversion 0x00 8060 — —
23 Timer 4 Update/overflow 0x00 8064 — —
24 EEPROM
End of programming/
write in not allowed area
0x00 8068 — —
1. All unused interrupts must be initialized with ‘IRET’ for robust programming.