Datasheet

Memory and register map STM8AF52/62xx, STM8AF51/61xx
48/110 Doc ID 14395 Rev 9
0x00 5437 beCAN CAN_PF CAN paged register F 0xXX
(3)
0x00 5438 to
0x00 57FF
Reserved area (968 bytes)
1. Depends on the previous reset source.
2. Write only register.
3. If the bootloader is enabled, it is initialized to 0x00.
Table 16. General hardware register map (continued)
Address Block Register label Register name
Reset
status
Table 17. CPU/SWIM/debug module/interrupt controller registers
Address Block Register label Register name
Reset
status
0x00 7F00
CPU
(1)
A Accumulator 0x00
0x00 7F01 PCE Program counter extended 0x00
0x00 7F02 PCH Program counter high 0x80
0x00 7F03 PCL Program counter low 0x00
0x00 7F04 XH X index register high 0x00
0x00 7F05 XL X index register low 0x00
0x00 7F06 YH Y index register high 0x00
0x00 7F07 YL Y index register low 0x00
0x00 7F08 SPH Stack pointer high 0x17
(2)
0x00 7F09 SPL Stack pointer low 0xFF
0x00 7F0A CC Condition code register 0x28
0x00 7F0B
to 0x00
7F5F
Reserved area (85 bytes)
0x00 7F60 CPU CFG_GCR Global configuration register 0x00
0x00 7F70
ITC
ITC_SPR1 Interrupt software priority register 1 0xFF
0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF
0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF
0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF
0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF
0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF
0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF
0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF
0x00 7F78
to
0x00 7F79
Reserved area (2 bytes)
0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00