Datasheet

Memory and register map STM8AF52/62xx, STM8AF51/61xx
46/110 Doc ID 14395 Rev 9
0x00 5320
TIM3
TIM3_CR1 TIM3 control register 1 0x00
0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00
0x00 5322 TIM3_SR1 TIM3 status register 1 0x00
0x00 5323 TIM3_SR2 TIM3 status register 2 0x00
0x00 5324 TIM3_EGR TIM3 event generation register 0x00
0x00 5325 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00
0x00 5326 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00
0x00 5327 TIM3_CCER1
TIM3 capture/compare enable register
1
0x00
0x00 5328 TIM3_CNTRH TIM3 counter high 0x00
0x00 5329 TIM3_CNTRL TIM3 counter low 0x00
0x00 532A TIM3_PSCR TIM3 prescaler register 0x00
0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF
0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF
0x00 532D TIM3_CCR1H TIM3 capture/compare register 1 high 0x00
0x00 532E TIM3_CCR1L TIM3 capture/compare register 1 low 0x00
0x00 532F TIM3_CCR2H TIM3 capture/compare register 2 high 0x00
0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00
0x00 5331 to
0x00 533F
Reserved area (15 bytes)
0x00 5340
TIM4
TIM4_CR1 TIM4 control register 1 0x00
0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00
0x00 5342 TIM4_SR TIM4 status register 0x00
0x00 5343 TIM4_EGR TIM4 event generation register 0x00
0x00 5344 TIM4_CNTR TIM4 counter 0x00
0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00
0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF
0x00 5347 to
0x00 53FF
Reserved area (185 bytes)
Table 16. General hardware register map (continued)
Address Block Register label Register name
Reset
status