Datasheet

STM8AF52/62xx, STM8AF51/61xx Memory and register map
Doc ID 14395 Rev 9 39/110
7.2 Register map
In this section the memory and register map of the devices covered by this datasheet is
described. For a detailed description of the functionality of the registers, refer to the
reference manual RM0016.
Table 15. I/O port hardware register map
Address Block Register label Register name
Reset
status
0x00 5000
Port A
PA_ODR Port A data output latch register 0x00
0x00 5001 PA_IDR Port A input pin value register 0xXX
(1)
0x00 5002 PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x00
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005
Port B
PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR Port B input pin value register 0xXX
(1)
0x00 5007 PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A
Port C
PC_ODR Port C data output latch register 0x00
0x00 500B PB_IDR Port C input pin value register 0xXX
(1)
0x00 500C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F
Port D
PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0xXX
(1)
0x00 5011 PD_DDR Port D data direction register 0x00
0x00 5012 PD_CR1 Port D control register 1 0x02
0x00 5013 PD_CR2 Port D control register 2 0x00
0x00 5014
Port E
PE_ODR Port E data output latch register 0x00
0x00 5015 PE_IDR Port E input pin value register 0xXX
(1)
0x00 5016 PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00
0x00 5019
Port F
PF_ODR Port F data output latch register 0x00
0x00 501A PF_IDR Port F input pin value register 0xXX
(1)
0x00 501B PF_DDR Port F data direction register 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00