Datasheet

Product overview STM8AF52/62xx, STM8AF51/61xx
26/110 Doc ID 14395 Rev 9
5.9.3 Serial peripheral interface (SPI)
The devices covered by this datasheet contain one SPI. The SPI is available on all the
supported packages.
● Maximum speed: 8 Mbit/s or f
MASTER
/2 both for master and slave
● Full duplex synchronous transfers
● Simplex synchronous transfers on two lines with a possible bidirectional data line
● Master or slave operation - selectable by hardware or software
● CRC calculation
● 1 byte Tx and Rx buffer
● Slave mode/master mode management by hardware or software for both master and
slave
● Programmable clock polarity and phase
● Programmable data order with MSB-first or LSB-first shifting
● Dedicated transmission and reception flags with interrupt capability
● SPI bus busy status flag
● Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– CRC error checking for last received byte
5.9.4 Inter integrated circuit (I
2
C) interface
The devices covered by this datasheet contain one I
2
C interface. The interface is available
on all the supported packages.
● I
2
C master features:
– Clock generation
– Start and stop generation
● I
2
C slave features:
– Programmable I
2
C address detection
– Stop bit detection
● Generation and detection of 7-bit/10-bit addressing and general call
● Supports different communication speeds:
– Standard speed (up to 100 kHz),
– Fast speed (up to 400 kHz)
● Status flags:
– Transmitter/receiver mode flag
– End-of-byte transmission flag
–I
2
C busy flag
● Error flags:
– Arbitration lost condition for master mode
– Acknowledgement failure after address/data transmission
– Detection of misplaced start or stop condition
– Overrun/underrun if clock stretching is disabled