Datasheet

Revision history STM8AF52/62xx, STM8AF51/61xx
108/110 Doc ID 14395 Rev 9
3&-Jan-2011
Rev 8
(continued)
Renamed Fast Active Halt mode to Active-halt mode with regulator
on, and Slow Active Halt mode to Active-halt mode with regulator off,
updated Section 5.6: Low-power operating modes, and Table 29:
Total current consumption in Halt and Active-halt modes. General
conditions for VDD applied. TA = -40 °C to 55 °C unless otherwise
stated. I
DD(FAH)
and I
DD(SAH)
renamed I
DD(AH);
t
WU(FAH)
and t
WU(SAH)
renamed t
WU(AH)
.
Removed note 1 in Table 26: General operating conditions, and note
1 below Figure 10: fCPUmax versus VDD.
Removed note 3 in Table 28: Total current consumption in Run, Wait
and Slow mode. General conditions for VDD apply, TA = -40 °C to
150 °C.
Removed note 2 in Table 33: HSE external clock characteristics and
Table 37: Flash program memory/data EEPROM memory.
Removed note 1 in Table 39: Data memory. Modified T
WE
maximum
value in Table 38: Flash program memory and Ta bl e 39: D a ta
memory.
Added t
IFP(NRST)
and renamed V
F(NRST)
t
IFP
in Table 41: NRST pin
characteristics.
Added recommendation concerning NRST pin level, and power
consumption sensitive applications, above Figure 38:
Recommended reset pin protection, and updated external capacitor
value.
Update Note 1 in Table 42: TIM 1, 2, 3, and 4 electrical
specifications.
Updated Note 1 in Table 43: SPI characteristics.
Moved know limitations to separate errata sheet.
Added “not recommended for new design” note to device family 51,
memory size 7 and 9, and temperature range B, in Figure 52:
Ordering information scheme(1).
Added Raisonance compiler in Section 13.2: Software tools.
18-Jul-2012 Rev 9
Updated wildcards of document part numbers.
Added VFQFPN package.
Added STM8AF62A6 part number.
Table 1: Device summary: updated footnote 1 and added footnote 2.
Table 2: STM8AF52xx product line-up with CAN and Ta b l e 3 :
STM8AF62xx product line-up without CAN: added “P” version for all
order codes; updated size of data EEPROM for 64K devices to 2K
instead of 1.5K; updated RAM.
Figure 1: STM8A block diagram: updated POR, BOR and WDG;
removed PDR; added legend.
Section 5.4: Flash program and data EEPROM: removed
nonrelevant bullet points and added a sentence about the factory
programme.
Added Table 6: Peripheral clock gating bits (CLK_PCKENR1) and
updated Table 7: Peripheral clock gating bits (CLK_PCKENR2).
ADC features: updated ADC input range.
Table 14: Memory model 128K: updated RAM size, RAM end
addresses, and stack roll-over addresses; updated footnote 1.
Table 57. Document revision history (continued)
Date Revision Changes