Datasheet

STM8AF52/62xx, STM8AF51/61xx Revision history
Doc ID 14395 Rev 9 107/110
3&-Jan-2011 Rev 8
Modified references to reference manual, and Flash programming
manual in the whole document.
Added reference to AEC Q100 standard on cover page.
Renamed timer types as follows:
– Auto-reload timer to general purpose timer
– Multipurpose timer to advanced control timer
– System timer to basic timer
Introduced concept of high density Flash program memory.
Updated number of I/Os for devices in 80-, 64-, and 48-pin packages
in Table 2: STM8AF52xx product line-up with CAN, Table 3:
STM8AF62xx product line-up without CAN, Ta bl e 4:
STM8AF/H/P51xx product line-up with CAN, and Ta b l e 5 :
STM8AF/H/P61xx product line-up without CAN.
Added TMU brief description in Section 5.4: Flash program and data
EEPROM, updated TMU_MAXATT description in Table 21: Option
byte description, and TMU_MAWATT reset value in Table 20: Option
bytes.
Updated clock sources in clock controller features (Section 5.5.1).
Added Table 7: Peripheral clock gating bits (CLK_PCKENR2) in
Section 5.5.6.
Added calibration using TIM3 in Section 5.7.2: Auto-wakeup counter.
Added Table 10: ADC naming and Table 11: Communication
peripheral naming correspondence.
Updated SPI data rate to f
MASTER
/2 in Section 5.9.3: Serial
peripheral interface (SPI).
Added reset state in Table 12: Legend/abbreviation for the pin
description table.
Table 13: STM8A microcontroller family pin description: modified
Note 2, added Note 3 related to PD1/SWIM, corrected wpu input for
PE1 and PE2, and renamed TIMn_CCx and TIMn_NCCx to
TIMn_CHx and TIMn_CHxN, respectively.
Section 7.2: Register map: Removed CAN register CLK_CANCCR.
Removed I2C_PECR register.
Added Note 1 for Px_IDR registers in Table 15: I/O port hardware
register map. Updated register reset values for Px_IDR and PD_CR1
registers.
Replaced tables describing register maps and reset values for non-
volatile memory, global configuration, reset status, TMU, clock
controller, interrupt controller, timers, communication interfaces, and
ADC, by Table 16: General hardware register map. Added debug
module register map.
Table 57. Document revision history (continued)
Date Revision Changes