Datasheet

STM8AF52/62xx, STM8AF51/61xx Revision history
Doc ID 14395 Rev 9 103/110
22-Aug-2008
Rev 2
cont’d
Table 35 : Removed ACC
HSI
parameters and replaced with ACC
HS
parameters; amended data and footnotes.
Amended data of ‘RAM and hardware registers’ table.
Table 37 : Updated names and data of N
RW
and t
RET
parameters.
Table 40 : Added V
OH
and V
OL
parameters; Updated I
lkg ana
parameter.
Removed: Output driving current (standard ports), Output driving
current (true open drain ports), and Output driving current (high sink
ports).
Table 45 : Updated f
ADC
, t
S
, and t
CONV
data.
ADC accuracy for V
DDA
= 3.3 V table: Removed the 4-MHz condition
from all parameters.
Table 46 : Removed the 4-MHz condition from all parameters;
updated footnote 1 and removed footnote 2.
Table 50 : Added data for T
A
= 145 °C.
Figure 52: Updated memory size, pin count and package type
information.
16-Sep-2008 Rev 3
Replaced the salestype ‘STM8H61xx’ with ‘STM8AH61xx on the first
page.
Added ‘part numbers’ to heading rows of Table 1: Device summary.
Updated the 80-pin package silhouette on page 1 in line with POA
0062342-revD.
Table 18 : Renamed ‘TMU key registers 0-7 [7:0]’ as ‘TMU key
registers 1-8 [7:0]’
Section 9: Updated introductory text concerning option bytes which
do not need to be saved in a complementary form.
Table 18 : Renamed the option bits ‘TMU[0:3]’, ‘NTMU[0:3]’, and
‘TMU_KEY 0-7 [7:0]’ as ‘TMU[3:0]’, ‘NTMU[3:0]’, and ‘TMU_KEY 1-8
[7:0]’ respectively.
Table 21 : Updated values of option byte 5 (HSECNT[7:0]); inverted
the description of option byte 6 (TMU[3:0]); renamed option bytes 8
to 15 ‘TMU_KEY 0-7 [7:0]’, as ‘TMU_KEY 1-8 [7:0]’.
Updated 80-pin package information in line with POA 0062342-revD
in Figure 44 and Table 5 2.
Table 57. Document revision history (continued)
Date Revision Changes