Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 8-Bit 24 MHz I/O number 52

This is information on a product in full production.

July 2012 Doc ID 14395 Rev 9 1/110

STM8AF5xxx STM8AF6x69/7x/8x/9x/Ax

Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM,

10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V

Datasheet − production data

Features

■ Core

–Max f

CPU

: 24 MHz

– Advanced STM8A core with Harvard

architecture and 3-stage pipeline

– Average 1.6 cycles/instruction resulting in

10 MIPS at 16 MHz f

CPU

for industry

standard benchmark

■ Memories

– Program memory: 32 to 128 Kbytes Flash

program; data retention 20 years at 55 °C

– Data memory: up to 2 Kbytes true data

EEPROM; endurance 300 kcycles

– RAM: 2 Kbytes to 6 Kbytes

■ Clock management

– Low-power crystal resonator oscillator with

external clock input

– Internal, user-trimmable 16 MHz RC and

low-power 128 kHz RC oscillators

– Clock security system with clock monitor

■ Reset and supply management

– Wait/auto-wakeup/Halt low-power modes

with user definable clock gating

– Low consumption power-on and power-

down reset

■ Interrupt management

– Nested interrupt controller with 32 vectors

– Up to 37 external interrupts on 5 vectors

■ Timers

– 2 general purpose 16-bit timers with up to 3

CAPCOM channels each (IC, OC, PWM)

– Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-

time insertion and flexible synchronization

– 8-bit AR basic timer with 8-bit prescaler

– Auto-wakeup timer

– Window and independent watchdog timers

■ I/Os

– Up to 68 user pins (11 high sink I/Os)

– Highly robust I/O design, immune against

current injection

■ Communication interfaces

– High speed 1 Mbit/s CAN 2.0B interface

– USART with clock output for synchronous

operation - LIN master mode

– LINUART LIN 2.1 compliant, master/slave

modes with automatic resynchronization

– SPI interface up to 10 Mbit/s or f

MASTER

–I

C interface up to 400 Kbit/s

■ Analog to digital converter (ADC)

– 10-bit resolution, 2 LSB TUE, 1 LSB

linearity and up to 16 multiplexed channels

■ Operating temperature up to 150 °C

■ Qualification conforms to AEC-Q100 rev G

Table 1. Device summary

(1)

In the order code, ‘F’ applies to devices with Flash program

memory and data EEPROM while ‘H’ refers to devices with

Flash program memory only. ‘F’ is replaced by ‘P’ for devices

with FASTROM (see Tables 2, 3, 4, and 5, and Figure 52).

Part numbers: STM8AF52xx (with CAN)

STM8AF52AA, STM8AF52A9, STM8AF52A8, STM8AF528A,

STM8AF5289, STM8AF5288, STM8AF5269, STM8AF5268

Part numbers: STM8AF6269/8x/Ax

STM8AF62AA, STM8AF62A9, STM8AF62A8, STM8AF628A,

STM8AF6289, STM8AF6288, STM8AF6286, STM8AF6269,

STM8AF62A6,

Part numbers: STM8AF51xx

(with CAN)

(2)

2. Not recommended for new design.

STM8AF51AA, STM8AF51A9, STM8AF51A8, STM8AF519A,

STM8AF5199, STM8AF5198, STM8AF518A, STM8AF5189,

STM8AF5188, STM8AF5179, STM8AF5178, STM8AF5169,

STM8AF5168

Part numbers: STM8AF6169/7x/8x/9x/Ax

(2)

STM8AF61AA, STM8AF61A9, STM8AF61A8, STM8AF619A,

STM8AF6199, STM8AF6198, STM8AF618A, STM8AF6189,

STM8AF6188, STM8AF6186, STM8AF6179, STM8AF6178,

STM8AF6176, STM8AF6169

LQFP80 14x14

LQFP48 7x7

LQFP32 7x7

VFQFPN32 5x5

LQFP64 10x10

www.st.com

Summary of content (110 pages)

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STM8AF5xxx STM8AF6x69/7x/8x/9x/Ax Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V Datasheet − production data Features ■ Core – Max fCPU: 24 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline – Average 1.
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Contents STM8AF52/62xx, STM8AF51/61xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8AF52/62xx, STM8AF51/61xx 7 5.7.4 Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 21 5.7.5 Basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.8 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.9 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.10 6 Contents 5.9.
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Contents STM8AF52/62xx, STM8AF51/61xx 10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.3.8 TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 77 10.3.9 SPI interface . . . . . . . . .
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STM8AF52/62xx, STM8AF51/61xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
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List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. 6/110 STM8AF52/62xx, STM8AF51/61xx EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . .
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STM8AF52/62xx, STM8AF51/61xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
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List of figures Figure 49. Figure 50. Figure 51. Figure 52. 8/110 STM8AF52/62xx, STM8AF51/61xx LQFP 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP 32-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5). . . . . . . . . . . . . . . 97 Ordering information scheme(1) . . . . . . . . . . . . . . . . . . . . . . . .
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STM8AF52/62xx, STM8AF51/61xx 1 Introduction Introduction This datasheet refers to the STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx products with 32 to 128 Kbytes of program memory. In the order code, the letter ‘F’ refers to product versions with Flash and data EEPROM, ‘H’ to product versions with Flash only, and ‘P’ to product versions with FASTROM. The identifiers ‘F’, ‘H’, and ‘P’ do not coexist in a given order code.
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Description 2 STM8AF52/62xx, STM8AF51/61xx Description The STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx automotive 8-bit microcontrollers described in this datasheet offer from 32 Kbytes to 128 Kbytes of non volatile memory and integrated true data EEPROM. They are referred to as high density STM8A devices in the STM8S and STM8A microcontroller families reference manual (RM0016). The STM8AF51xx and STM8AF52xx series feature a CAN interface.
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STM8AF52/62xx, STM8AF51/61xx Product line-up 3 Product line-up Table 2. STM8AF52xx product line-up with CAN .. Order code Package STM8AF/P52AA LQFP80 (14x14) STM8AF/P528A High density Flash program memory (bytes) Data RAM EEPROM (bytes) (bytes) 10-bit A/D chan. Timers (IC/OC/PWM) Serial interfaces I/0 wakeup pins 128 K 68/37 64 K 2K STM8AF/P52A9 STM8AF/P5289 LQFP64 (10x10) STM8AF/P5269 6K 1K 128 K LQFP48 (7x7) STM8AF/P5268 Table 3.
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Product line-up . Table 4. STM8AF52/62xx, STM8AF51/61xx STM8AF/H/P51xx product line-up with CAN Order code Package STM8AF/H/P51AA STM8AF/H/P519A High density Flash program memory (bytes) Data RAM EEPROM (bytes) (bytes) 10-bit A/D chan. Timers (IC/OC/PWM) Serial interfaces I/0 wakeup pins 128 K LQFP80 (14x14) 96 K STM8AF/H/P518A 64 K STM8AF/H/P51A9 128 K STM8AF/H/P5199 96 K 68/37 6K 2K 16 STM8AF/H/P5189 LQFP64 (10x10) 64 K 1.
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STM8AF52/62xx, STM8AF51/61xx ² Table 5. Product line-up STM8AF/H/P61xx product line-up without CAN Order code Package STM8AF/H/P61AA STM8AF/H/P619A High density Data Flash RAM EEPROM program (bytes) (bytes) memory (bytes) 10-bit A/D chan. Timers (IC/OC/PWM) I/0 Serial wakeup interfaces pins 128 K LQFP80 (14x14) 96 K STM8AF/H/P618A 64 K STM8AF/H/P61A9 128 K STM8AF/H/P6199 96 K 68/37 6K 2K 16 STM8AF/H/P6189 LQFP64 (10x10) 64 K 4K 1.
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Block diagram 4 STM8AF52/62xx, STM8AF51/61xx Block diagram Figure 1. STM8A block diagram Reset block XTAL 1-24 MHz Clock controller Reset Reset RC int. 16 MHz Detector POR RC int. 128 kHz BOR Clock to peripherals and core Window WDG STM8A CORE IWDG Master/slave automatic resynchronization 400 Kbit/s 10 Mbit/s Up to 128 Kbyte high density program Flash Debug/SWIM LINUART I2C SPI Address and data bus Single wire debug interf.
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STM8AF52/62xx, STM8AF51/61xx 5 Product overview Product overview This section is intended to describe the family features that are actually implemented in the products covered by this datasheet. For more detailed information on each feature please refer to the STM8S and STM8A microcontroller families reference manual (RM0016). 5.1 STM8A central processing unit (CPU) The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency and performance.
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Product overview STM8AF52/62xx, STM8AF51/61xx 5.2 Single wire interface module (SWIM) and debug module (DM) 5.2.1 SWIM The single wire interface module, SWIM, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. The interface can be activated in all device operation modes and can be connected to a running device (hot plugging).The maximum data transmission speed is 145 bytes/ms. 5.2.
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STM8AF52/62xx, STM8AF51/61xx 5.4.2 Product overview Write protection (WP) Write protection in application mode is intended to avoid unintentional overwriting of the memory. The write protection can be removed temporarily by executing a specific sequence in the user software. 5.4.
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Product overview STM8AF52/62xx, STM8AF51/61xx If desired, the temporary unlock mechanism can be permanently disabled by the user through OPT6/NOPT6 option bytes. 5.5 Clock controller The clock controller distributes the system clock coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. 5.5.1 Features ● 5.5.
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STM8AF52/62xx, STM8AF51/61xx 5.5.3 Product overview 128 kHz low-speed internal RC oscillator (LSI) The frequency of this clock is 128 kHz and it is independent from the main clock. It drives the independent watchdog or the AWU wakeup timer. In systems which do not need independent clock sources for the watchdog counters, the 128 kHz signal can be used as the system clock. This configuration has to be enabled by setting an option byte (OPT3/OPT3N, bit LSI_EN). 5.5.
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Product overview Table 7. 5.6 STM8AF52/62xx, STM8AF51/61xx Peripheral clock gating bits (CLK_PCKENR2) Control bit Peripheral PCKEN27 CAN PCKEN26 Reserved PCKEN25 Reserved PCKEN24 Reserved PCKEN23 ADC PCKEN22 AWU PCKEN21 Reserved PCKEN20 Reserved Low-power operating modes For efficient power management, the application can be put in one of four different lowpower modes.
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STM8AF52/62xx, STM8AF51/61xx 5.7 Timers 5.7.1 Watchdog timers Product overview The watchdog system is based on two independent timers providing maximum security to the applications. The watchdog timer activity is controlled by the application program or option bytes. Once the watchdog is activated, it cannot be disabled by the user program without going through reset.
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Product overview Table 8.
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STM8AF52/62xx, STM8AF51/61xx 5.8 Product overview Analog to digital converter (ADC) The STM8A products described in this datasheet contain a 10-bit successive approximation ADC with up to 16 multiplexed input channels, depending on the package. The ADC name differs between the datasheet and the STM8A/S reference manual (see Table 10). Table 10. ADC naming Peripheral name in datasheet Peripheral name in reference manual (RM0016) ADC ADC2 ADC features 5.
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Product overview STM8AF52/62xx, STM8AF51/61xx Detailed feature list: ● Full duplex, asynchronous communications ● NRZ standard format (mark/space) ● High-precision baud rate generator system – ● Programmable data word length (8 or 9 bits) ● Configurable stop bits: Support for 1 or 2 stop bits ● LIN master mode: – LIN break and delimiter generation – LIN break and delimiter detection with separate flag and interrupt source for readback checking.
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STM8AF52/62xx, STM8AF51/61xx 5.9.2 Product overview Universal asynchronous receiver/transmitter with LIN support (LINUART) The devices covered by this datasheet contain one LINUART interface. The interface is available on all the supported packages. The LINUART is an asynchronous serial communication interface which supports extensive LIN functions tailored for LIN slave applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.1.
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Product overview 5.9.3 STM8AF52/62xx, STM8AF51/61xx Serial peripheral interface (SPI) The devices covered by this datasheet contain one SPI. The SPI is available on all the supported packages. 5.9.
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STM8AF52/62xx, STM8AF51/61xx ● ● 5.9.5 Product overview Interrupt: – Successful address/data communication – Error condition – Wakeup from Halt Wakeup from Halt on address detection in slave mode Controller area network interface (beCAN) The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the CAN protocol version 2.0A and B. It is equipped with a receive FIFO and a very versatile filter bank.
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Product overview 5.10 STM8AF52/62xx, STM8AF51/61xx Input/output specifications The product features four I/O types: ● Standard I/O 2 MHz ● Fast I/O up to 10 MHz ● High sink 8 mA, 2 MHz ● True open drain (I2C interface) To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum slew rate. The rise and fall times are similar to those of standard I/Os. The analog inputs are equipped with a low leakage analog switch.
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STM8AF52/62xx, STM8AF51/61xx Pinouts and pin description 6 Pinouts and pin description 6.1 Package pinouts LQFP 80-pin pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CH1/BEEP PD3 (HS)/TIM2_CH2 PD2 (HS)/TIM3_CH1 PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 PI7 PI6 PE0/CLK_CCO PE1/I2C_SCL PE2/I 2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 PI5 PI4 Figure 3.
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Pinouts and pin description LQFP 64-pin pinout PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CH1/ BEEP PD3 (HS)/TIM2_CH2/ADC_ETR PD2 (HS)/TIM3_CH1 PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 PE0/CLK_CCO PE1/I2C_SCL PE2/I2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 Figure 4.
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STM8AF52/62xx, STM8AF51/61xx LQFP 48-pin pinout PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CH1/BEEP PD3 (HS)/TIM2_CH2/ADC_ETR PD2 (HS)/TIM3_CH1 PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 PE0/CLK_CCO PE1/I2C_SCL PE2/I2C_SDA PE3/TIM1_BKIN Figure 5.
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Pinouts and pin description LQFP/VFQFPN 32-pin pinout PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CH1/BEEP PD3 (HS)/TIM2_CH2/ADC_ETR PD2 (HS)/TIM3_CH1/TIM2_CH3 PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2/CLK_CCO/TIM1_BRK Figure 6.
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STM8AF52/62xx, STM8AF51/61xx Table 13. Pinouts and pin description STM8A microcontroller family pin description LQFP48 LQFP32/VFQFPN32 Type floating wpu Ext.
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Pinouts and pin description Table 13. STM8AF52/62xx, STM8AF51/61xx STM8A microcontroller family pin description (continued) floating wpu Ext.
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STM8AF52/62xx, STM8AF51/61xx Table 13. Pinouts and pin description STM8A microcontroller family pin description (continued) Input wpu Ext.
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Pinouts and pin description Table 13. STM8AF52/62xx, STM8AF51/61xx STM8A microcontroller family pin description (continued) LQFP32/VFQFPN32 floating wpu Ext.
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STM8AF52/62xx, STM8AF51/61xx Pinouts and pin description 1. In Halt/Active-halt mode, this pin behaves as follows: - The input/output path is disabled. - If the HSE clock is used for wakeup, the internal weak pull-up is disabled. - If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in Halt/Active-halt mode. 2.
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Memory and register map STM8AF52/62xx, STM8AF51/61xx 7 Memory and register map 7.1 Memory map Figure 7. Register and memory map 00 0000 Up to 6 Kbytes RAM Stack RAM end address Reserved 00 4000 Up to 2 Kbytes data EEPROM 00 4800 Option bytes 00 4900 00 5000 Reserved HW registers 00 5800 Reserved 00 6000 2 Kbytes boot ROM 00 6800 00 7F00 CPU/SWIM/Debug/ITC registers 00 8000 IT vectors 00 8080 Up to 128 Kbytes Flash program memory Memory end address Table 14.
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STM8AF52/62xx, STM8AF51/61xx 7.2 Memory and register map Register map In this section the memory and register map of the devices covered by this datasheet is described. For a detailed description of the functionality of the registers, refer to the reference manual RM0016. Table 15.
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Memory and register map Table 15.
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STM8AF52/62xx, STM8AF51/61xx Table 16.
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Memory and register map Table 16.
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STM8AF52/62xx, STM8AF51/61xx Table 16.
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Memory and register map Table 16.
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STM8AF52/62xx, STM8AF51/61xx Table 16.
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Memory and register map Table 16.
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STM8AF52/62xx, STM8AF51/61xx Table 16.
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Memory and register map Table 16. STM8AF52/62xx, STM8AF51/61xx General hardware register map (continued) Address Block Register label Register name Reset status 0x00 5437 beCAN CAN_PF CAN paged register F 0xXX(3) 0x00 5438 to 0x00 57FF Reserved area (968 bytes) 1. Depends on the previous reset source. 2. Write only register. 3. If the bootloader is enabled, it is initialized to 0x00. Table 17.
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STM8AF52/62xx, STM8AF51/61xx Table 17.
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Interrupt table STM8AF52/62xx, STM8AF51/61xx 8 Interrupt table Table 19.
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STM8AF52/62xx, STM8AF51/61xx 9 Option bytes Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Each option byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.
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Option bytes Table 20. Addr. STM8AF52/62xx, STM8AF51/61xx Option bytes (continued) Option name 0x00 480B Option byte no.
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STM8AF52/62xx, STM8AF51/61xx Table 21. Option bytes Option byte description Option byte no. Description OPT0 ROP[7:0]: Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the STM8A microcontroller family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details.
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Option bytes STM8AF52/62xx, STM8AF51/61xx Table 21. Option byte description (continued) Option byte no.
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STM8AF52/62xx, STM8AF51/61xx Table 21. Option bytes Option byte description (continued) Option byte no.
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Electrical characteristics STM8AF52/62xx, STM8AF51/61xx 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.
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STM8AF52/62xx, STM8AF51/61xx 10.1.5 Electrical characteristics Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9. Figure 9. Pin input voltage STM8A pin VIN 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied.
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Electrical characteristics Table 23. STM8AF52/62xx, STM8AF51/61xx Current characteristics Symbol Ratings Max. IVDDIO Total current into VDDIO power lines (source)(1)(2)(3) 100 IVSSIO (1)(2)(3) 100 Total current out of VSS IO ground lines (sink) IIO Output current sunk by any I/O and control pin 20 Output current source by any I/Os and control pin -20 Injected current on any pin ±10 Sum of injected currents 50 Unit mA IINJ(PIN)(4) IINJ(TOT) 1.
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STM8AF52/62xx, STM8AF51/61xx 10.3 Electrical characteristics Operating conditions Table 26. General operating conditions Symbol Parameter fCPU Internal CPU clock frequency VDD/VDDIO Conditions Min Max 1 wait state TA = -40 °C to 150 °C 16 24 0 wait state TA = -40 °C to 150 °C 0 16 - 3.0 5.5 V 470 3300 nF - 0.
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Electrical characteristics Table 27. tTEMP Parameter Conditions Min Typ Max — 2(1) — — (1) 2 — 8 tVDD Operating conditions at power-up/power-down 8 Symbol STM8AF52/62xx, STM8AF51/61xx VDD rise time rate VDD fall time rate Unit µs/V Reset release delay VDD rising — 3 — ms Reset generation delay VDD falling — 3 — µs VIT+ Power-on reset threshold(2) — 2.65 2.8 2.95 VIT- Brown-out reset threshold — 2.58 2.73 2.
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STM8AF52/62xx, STM8AF51/61xx Table 28. Total current consumption in Run, Wait and Slow mode.
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Electrical characteristics Table 29. STM8AF52/62xx, STM8AF51/61xx Total current consumption in Halt and Active-halt modes. General conditions for VDD applied.
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STM8AF52/62xx, STM8AF51/61xx Table 31. Symbol IDD(PROG) Table 32. Symbol IDD(TIM1) Electrical characteristics Programming current consumption Parameter Programming current Conditions Typ Max Unit VDD = 5 V, -40 °C to 150 °C, erasing and programming data or Flash program memory 1.0 1.7 mA Typical peripheral current consumption VDD = 5.0 V(1) Parameter TIM1 supply current(2) Typ. Typ. 0.03 0.23 0.34 0.02 0.12 0.19 IDD(TIM3) TIM3 supply current(2) 0.01 0.1 0.
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Electrical characteristics STM8AF52/62xx, STM8AF51/61xx Current consumption curves Figure 12 to Figure 17 show typical current consumption measured with code executing in RAM. Figure 12. Typ. IDD(RUN)HSE vs. VDD @fCPU = 16 MHz, peripherals = on 10 9 25°C 8 85°C 7 125°C 25°C 9 IDD(RUN)HSE [mA] IDD(RUN)HSE [mA] 10 Figure 13. Typ. IDD(RUN)HSE vs. fCPU @ VDD = 5.0 V, peripherals = on 6 5 4 3 2 1 8 85°C 7 125°C 6 5 4 3 2 1 0 0 2.5 3 3.5 4 4.5 5 5.
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STM8AF52/62xx, STM8AF51/61xx 10.3.3 Electrical characteristics External clock sources and timing characteristics HSE external clock An HSE clock can be generated by feeding an external clock signal of up to 24 MHz to the OSCIN pin. Clock characteristics are subject to general operating conditions for VDD and TA. Table 33.
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Electrical characteristics Table 34. HSE oscillator characteristics Symbol Parameter RF CL1/CL2 STM8AF52/62xx, STM8AF51/61xx (1) gm tSU(HSE)(2) Conditions Min Typ Max Unit Feedback resistor — — 220 — kΩ Recommended load capacitance — — — 20 pF Oscillator trans conductance — 5 — — mA/V VDD is stabilized — 2.8 — ms Startup time 1. The oscillator needs two load capacitors, CL1 and CL2, to act as load for the crystal.
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STM8AF52/62xx, STM8AF51/61xx Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. High-speed internal RC oscillator (HSI) Table 35. HSI oscillator characteristics Symbol fHSI Parameter Conditions Min Typ Max Unit — — 16 — MHz HSI oscillator user trimming accuracy Trimmed by the application for any VDD and TA conditions -1 — 1 HSI oscillator accuracy (factory calibrated) VDD = 3.0 V ≤ VDD ≤ 5.
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Electrical characteristics STM8AF52/62xx, STM8AF51/61xx Low-speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 36. LSI oscillator characteristics Symbol fLSI tsu(LSI) Parameter Conditions Min Typ Max Unit Frequency — 112 128 144 kHz LSI oscillator wakeup time — — — 7(1) µs 1. Data based on characterization results, not tested in production. Figure 21.
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STM8AF52/62xx, STM8AF51/61xx 10.3.5 Electrical characteristics Memory characteristics Flash program memory/data EEPROM memory General conditions: TA = -40 °C to 150 °C. Table 37. Symbol VDD Flash program memory/data EEPROM memory Parameter Conditions Min(1) Typ Max Operating voltage (all modes, execution/write/erase) fCPU is 16 to 24 MHz with 1 ws fCPU is 0 to 16 MHz with 0 ws Operating voltage (code execution) fCPU is 16 to 24 MHz with 1 ws fCPU is 0 to 16 MHz with 0 ws 2.6 — 5.
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Electrical characteristics Table 39. STM8AF52/62xx, STM8AF51/61xx Data memory Symbol Parameter Condition Min Max Unit TWE Temperature for writing and erasing — -40 150 °C Data memory endurance(1) (erase/write cycles) TA = 25 °C 300 k NWE tRET Data retention time — cycles (2) 100 k — TA = 25 °C 40(2)(3) — TA = 55 °C (2)(3) — TA = -40°C to 125 °C 20 years 1.
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STM8AF52/62xx, STM8AF51/61xx 10.3.6 Electrical characteristics I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 40.
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Electrical characteristics STM8AF52/62xx, STM8AF51/61xx 2. Guaranteed by design. 3. Data based on characterization results, not tested in production. Figure 22. Typical VIL and VIH vs VDD @ four temperatures 6 -40°C 25°C 5 85°C VIL / V IH [V] 4 125°C 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 23. Typical pull-up resistance RPU vs VDD @ four temperatures 60 Pull-Up resistance [k ohm] 55 50 45 -40°C 40 25°C 85°C 35 125°C 30 2.5 3 3.5 4 4.
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STM8AF52/62xx, STM8AF51/61xx Electrical characteristics Figure 24. Typical pull-up current Ipu vs VDD @ four temperatures(1) 140 Pull-Up current [µA] 120 100 80 -40°C 60 25°C 40 85°C 125°C 20 0 0 1 2 3 4 5 6 VDD [V] 1. The pull-up is a pure resistor (slope goes through 0). Typical output level curves Figure 25 to Figure 34 show typical output level curves measured with output on a single pin. Figure 25. Typ. VOL @ VDD = 3.3 V (standard ports) Figure 26. Typ. VOL @ VDD = 5.
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Electrical characteristics STM8AF52/62xx, STM8AF51/61xx Figure 29. Typ. VOL @ VDD = 3.3 V (high sink ports) Figure 30. Typ. VOL @ VDD = 5.0 V (high sink ports) -40°C 1.5 25°C 85°C 1.25 -40°C 1.5 25°C 85°C 1.25 125°C 125°C 1 VOL [V] VOL [V] 1 0.75 0.75 0.5 0.5 0.25 0.25 0 0 0 2 4 6 8 10 12 14 0 5 10 IOL [mA] Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) 125°C 85°C 125°C 1.5 1.25 VDD - V OH [V] VDD - V OH [V] 25°C 1.75 85°C 1.5 1 0.75 1.25 1 0.75 0.
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STM8AF52/62xx, STM8AF51/61xx Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 41. NRST pin characteristics Symbol VIL(NRST) Parameter Conditions Min Typ Max — VSS — 0.3 x VDD — 0.7 x VDD — VDD — 0.
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Electrical characteristics STM8AF52/62xx, STM8AF51/61xx Figure 36. Typical NRST pull-up resistance RPU vs VDD -40°C 60 NRST Pull-Up resistance [k ohm] 25°C 55 85°C 125°C 50 45 40 35 30 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 37. Typical NRST pull-up current Ipu vs VDD 140 NRST Pull-Up current [µA] 120 100 80 60 -40°C 25°C 40 85°C 20 125°C 0 0 1 2 3 VDD [V] 4 5 6 The reset network shown in Figure 38 protects the device against parasitic resets.
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STM8AF52/62xx, STM8AF51/61xx Electrical characteristics Figure 38. Recommended reset pin protection STM8A VDD RPU External reset circuit (optional) NRST Internal reset Filter 0.1µF 10.3.8 TIM 1, 2, 3, and 4 electrical specifications Subject to general operating conditions for VDD, fMASTER and TA. Table 42. TIM 1, 2, 3, and 4 electrical specifications Symbol fEXT Parameter Conditions Min Typ Max Unit — — — 24 MHz Timer external clock frequency(1) 1. Not tested in production.
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Electrical characteristics STM8AF52/62xx, STM8AF51/61xx SPI interface 10.3.9 Unless otherwise specified, the parameters given in Table 43 are derived from tests performed under ambient temperature, fMASTER frequency, and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 43.
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STM8AF52/62xx, STM8AF51/61xx Electrical characteristics Figure 39. SPI timing diagram in slave mode and with CPHA = 0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT M SB IN LSB IN B I T1 IN th(SI) ai14134 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 40.
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Electrical characteristics STM8AF52/62xx, STM8AF51/61xx Figure 41. SPI timing diagram - master mode (IGH .33 INPUT 3#+ OUTPUT #0(! #0/, 3#+ OUTPUT TC 3#+ #0(! #0/, #0(! #0/, #0(! #0/, TSU -) -)3/ ).0 54 TW 3#+( TW 3#+, TR 3#+ TF 3#+ -3 "). ") 4 ). ,3" ). TH -) -/3) /5454 " ) 4 /54 - 3" /54 TV -/ ,3" /54 TH -/ AI 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
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STM8AF52/62xx, STM8AF51/61xx 10.3.10 Electrical characteristics I2C interface characteristics Table 44. I2C characteristics Standard mode I2C Fast mode I2C(1) Symbol Parameter Min(2) Max(2) Min(2) Max(2) Unit tw(SCLL) SCL clock low time 4.7 — 1.3 — tw(SCLH) SCL clock high time 4.0 — 0.6 — tsu(SDA) SDA setup time 250 — 100 — th(SDA) SDA data hold time 0(3) — 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time (VDD 3 V to 5.
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Electrical characteristics 10.3.11 STM8AF52/62xx, STM8AF51/61xx 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER and TA unless otherwise specified. Table 45. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit kHz/MHz fADC ADC clock frequency — 111 kHz — 4 MHz VDDA Analog supply — 3 — 5.5 VREF+ Positive reference voltage — 2.75 — VDDA VREF- Negative reference voltage — VSSA — 0.
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STM8AF52/62xx, STM8AF51/61xx Table 46. Electrical characteristics ADC accuracy for VDDA = 5 V Symbol Parameter Conditions Typ Max(1) |ET| Total unadjusted error(2) 1.4 3(3) |EO| Offset error(2) 0.8 3 0.1 2 0.9 1 0.7 1.5 (2) |EG| Gain error |ED| Differential linearity error(2) |EL| fADC = 2 MHz Integral linearity error (2) (2) (4) 1.9 4(4) 1.3(4) 4(4) 0.
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Electrical characteristics 10.3.12 STM8AF52/62xx, STM8AF51/61xx EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
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STM8AF52/62xx, STM8AF51/61xx Electrical characteristics Electromagnetic interference (EMI) Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin loading. Table 48. EMI data Conditions Symbol SEMI Parameter Max fCPU(1) General conditions VDD = 5 V, TA = 25 °C, Peak level LQFP80 package conforming to SAE SAE EMI level J 1752/3 Monitored frequency band Unit 8 MHz 16 MHz 24 MHz 0.
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Electrical characteristics STM8AF52/62xx, STM8AF51/61xx Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance. ● A supply overvoltage (applied to each power supply pin) and ● A current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 50.
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STM8AF52/62xx, STM8AF51/61xx 10.4 Electrical characteristics Thermal characteristics In case the maximum chip junction temperature (TJmax) specified in Table 26: General operating conditions is exceeded, the functionality of the device cannot be guaranteed.
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Electrical characteristics 10.4.2 STM8AF52/62xx, STM8AF51/61xx Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 52: Ordering information scheme(1) on page 98). The following example shows how to calculate the temperature range needed for a given application.
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STM8AF52/62xx, STM8AF51/61xx 11 Package characteristics Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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Package characteristics 11.1 STM8AF52/62xx, STM8AF51/61xx Package mechanical data Figure 44. LQFP 80-pin low profile quad flat package (14 x 14) D ccc C D1 A A2 D3 41 60 40 61 b L1 E3 E1 E L A1 K 80 Pin 1 identification Table 52. 1 c 1S_ME LQFP 80-pin low profile quad flat package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A — — 1.600 — — 0.0630 A1 0.050 — 0.150 0.0020 — 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.220 0.320 0.380 0.
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STM8AF52/62xx, STM8AF51/61xx Package characteristics Figure 45. LQFP 64-pin low profile quad flat package (10 x 10) D ccc C D1 A A2 D3 33 48 32 49 b L1 E3 E1 E L A1 K 64 17 Pin 1 identification 16 1 Table 53. c 5W_ME LQFP 64-pin low profile quad flat package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A — — 1.600 — — 0.0630 A1 0.050 — 0.150 0.0020 — 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.
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Package characteristics STM8AF52/62xx, STM8AF51/61xx Figure 46. LQFP 64-pin recommended footprint 7?&0 1. Drawing is not to scale. Dimensions are in millimeters.
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STM8AF52/62xx, STM8AF51/61xx Package characteristics Figure 47. LQFP 48-pin low profile quad flat package (7 x 7) D ccc C D1 D3 A A2 25 36 24 37 L1 b E3 E1 E 48 Pin 1 identification 13 1 L A1 K c 12 5B_ME Table 54. LQFP 48-pin low profile quad flat package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A — — 1.600 — — 0.0630 A1 0.050 — 0.150 0.0020 — 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.
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Package characteristics STM8AF52/62xx, STM8AF51/61xx Figure 48. LQFP 48-pin recommended footprint "?&0 1. Drawing is not to scale. Dimensions are in millimeters.
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STM8AF52/62xx, STM8AF51/61xx Package characteristics Figure 49. LQFP 32-pin low profile quad flat package (7 x 7) ccc C D D1 D3 24 A A2 17 16 25 L1 b E3 32 E1 E 9 Pin 1 identification L A1 1 K c 8 5V_ME Table 55. LQFP 32-pin low profile quad flat package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A — — 1.600 — — 0.0630 A1 0.050 — 0.150 0.0020 — 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.
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Package characteristics STM8AF52/62xx, STM8AF51/61xx Figure 50. LQFP 32-pin recommended footprint 6?&0 1. Drawing is not to scale. Dimensions are in millimeters.
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STM8AF52/62xx, STM8AF51/61xx Package characteristics Figure 51. VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5) Seating plane C ddd C A A1 A3 D e 16 9 17 8 E b E2 24 1 L 32 Pin # 1 ID R = 0.30 D2 L Bottom view Table 56. 42_ME VFQFPN 32-lead very thin fine pitch quad flat no-lead package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A 0.800 0.900 1.000 0.0315 0.0354 0.0394 A1 0.000 0.020 0.050 0.000 0.0008 0.0020 A3 — 0.
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Ordering information 12 STM8AF52/62xx, STM8AF51/61xx Ordering information Figure 52.
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STM8AF52/62xx, STM8AF51/61xx 13 STM8 development tools STM8 development tools Development tools for the STM8A microcontrollers include the ● STice emulation system offering tracing and code profiling ● STVD high-level language debugger including assembler and visual development environment - seamless integration of third party C compilers ● STVP Flash programming software In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. 13.
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STM8 development tools 13.2 STM8AF52/62xx, STM8AF51/61xx Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. 13.2.1 STM8 toolset The STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.
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STM8AF52/62xx, STM8AF51/61xx 13.3 STM8 development tools Programming tools During the development cycle, STice provides in-circuit programming of the STM8A Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8A.
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Revision history 14 STM8AF52/62xx, STM8AF51/61xx Revision history Table 57. Document revision history Date Revision 31-Jan-2008 Rev 1 Initial release Rev 2 Added ‘H’ products to the datasheet (Flash no EEPROM). Features on page 1: Updated Memories, Reset and supply management, Communication interfaces and I/Os; reduced wakeup pins by 1. Table 1: Removed STM8AF6168, STM8AF6148, STM8AF6166, STM8AF6146, STM8AF5168, STM8AF5186, STM8AF5176, and STM8AF5166. Section 1, Section 5, Section 6.
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STM8AF52/62xx, STM8AF51/61xx Table 57. Revision history Document revision history (continued) Date 22-Aug-2008 16-Sep-2008 Revision Changes Rev 2 cont’d Table 35: Removed ACCHSI parameters and replaced with ACCHS parameters; amended data and footnotes. Amended data of ‘RAM and hardware registers’ table. Table 37: Updated names and data of NRW and tRET parameters. Table 40: Added VOH and VOL parameters; Updated Ilkg ana parameter.
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Revision history STM8AF52/62xx, STM8AF51/61xx Table 57. Document revision history (continued) Date 01-Jul-2009 104/110 Revision Changes Rev 4 Added ‘STM8AH61xx’ and ‘STM8AH51xx to document header. Updated Features on page 1 (memories, timers, operating temperature, ADC and I/Os). Updated Table 1: Device summary. Updated Kbytes value of program memory in Chapter 1: Introduction Chapter 2: Description – Changed the first two lines from the top.
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STM8AF52/62xx, STM8AF51/61xx Table 57. Revision history Document revision history (continued) Date 01-Jul-2009 Revision Changes Rev 4 Removed Table 22: Total current consumption and timing in halt, fast active halt and slow active halt modes at VDD = 3.3 V. Added Table 30: Oscillator current consumption Added Table 31: Programming current consumption. Updated Table 32: Typical peripheral current consumption VDD = 5.
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Revision history STM8AF52/62xx, STM8AF51/61xx Table 57. Document revision history (continued) Date Revision 22-Oct-2009 Rev 5 Updated Table 1: Device summary: – Added STM8AF5178, STM8AF519A and STM8AF619A. Rev 6 Updated title on cover page. Modified cover page header to clarify the part numbers covered by the datasheets. Updated Note 1 below Table 1: Device summary to add ‘P’ order codes. Changed definition of ‘P’ order codes. ‘Q’ order codes (FASTROM and EEPROM) removed.
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STM8AF52/62xx, STM8AF51/61xx Table 57. Revision history Document revision history (continued) Date Revision Changes Modified references to reference manual, and Flash programming manual in the whole document. Added reference to AEC Q100 standard on cover page. Renamed timer types as follows: – Auto-reload timer to general purpose timer – Multipurpose timer to advanced control timer – System timer to basic timer Introduced concept of high density Flash program memory.
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Revision history STM8AF52/62xx, STM8AF51/61xx Table 57. Document revision history (continued) Date 3&-Jan-2011 18-Jul-2012 108/110 Revision Changes Rev 8 (continued) Renamed Fast Active Halt mode to Active-halt mode with regulator on, and Slow Active Halt mode to Active-halt mode with regulator off, updated Section 5.6: Low-power operating modes, and Table 29: Total current consumption in Halt and Active-halt modes. General conditions for VDD applied. TA = -40 °C to 55 °C unless otherwise stated.
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STM8AF52/62xx, STM8AF51/61xx Table 57. Revision history Document revision history (continued) Date 18-Jul-2012 Revision Changes Rev 9 (continued) Table 20: Option bytes: updated factory default setting for NOPT17; updated footnote 1. Table 22: Voltage characteristics: updated VDDX - VDD to VDDX - VSS. Table 26: General operating conditions: updated VCAP. Table 28: Total current consumption in Run, Wait and Slow mode.
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STM8AF52/62xx, STM8AF51/61xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.