Datasheet
DC and AC parameters STM690A/692A/703/704/802/805/817/818/819
36/43 Doc ID 10522 Rev 10
t
REC
RST pulse width 140 200 280 ms
Push-button reset input (STM703/704/819)
t
MLMH
t
MR
MR pulse width
STM703/704 150 ns
STM819 1 µs
t
MLMR
t
MRD
MR to RST output delay
STM703/704 250 ns
STM819 120 ns
MR
glitch immunity STM819 100 ns
MR
pull-up resistor MR = 0 V, V
CC
= 5 V 45 63 85 kΩ
Watchdog timer (NOT available on STM703/704/819)
t
WD
Watchdog timeout period V
RST
(max) < V
CC
< 5.5 V 1.12 1.60 2.24 s
WDI pulse width V
RST
(max) < V
CC
< 5.5 V 50 ns
Chip-enable gating (STM818 only)
E to E
CON
resistance V
CC
= V
RST
(max) 40 150 Ω
E
to E
CON
propagation
delay
4.5 V < V
CC
< 5.5 V 2 7 ns
Reset to E
CON
high delay (Power-down) 15 µs
E
CON
short circuit current
V
CC
= 5 V, disable mode,
E
= logic high, E
CON
= 0 V
0.1 0.75 2.0 mA
1. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 4.75 V to 5.5 V for “L” versions; V
CC
= 4.5 V to 5.5 V for
“M” versions; and V
BAT
= 2.8 V (except where noted).
2. V
CC
supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality, state of
RST and RST tested at V
BAT
= 3.6 V, and V
CC
= 5.5 V. The state of RST or RST and PFO is tested at V
CC
= V
CC
(min).
Either V
CC
or V
BAT
can go to 0 V if the other is greater than 2.0 V.
3. V
CC
(min) = 1.0 V for T
A
= 0 °C to +85 °C.
4. Tested at V
BAT
= 3.6 V, V
CC
= 3.5 V and 0 V.
5. Guaranteed by design.
6. WDI input is designed to be driven by a three-state output device. To float WDI, the “high impedance mode” of the output
device must have a maximum leakage current of 10 µA and a maximum output capacitance of 200 pF. The output device
must also be able to source and sink at least 200 µA when active.
7. When V
BAT
> V
CC
> V
RST
, V
OUT
remains connected to V
CC
until V
CC
drops below V
RST
.
8. When V
RST
> V
CC
> V
BAT
, V
OUT
remains connected to V
CC
until V
CC
drops below the battery voltage (V
BAT
) – 75 mV.
9. For V
CC
falling.
Table 7. DC and AC characteristics (continued)
Sym
Alter-
native
Description Test condition
(1)
Min Typ Max Unit