Datasheet

Description STM690A/692A/703/704/802/805/817/818/819
8/43 Doc ID 10522 Rev 10
Figure 5. STM703/704/819 connections
Figure 6. STM818 connections
1.1 Pin descriptions
1.1.1 MR
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for t
rec
after MR returns high. This active-low input has an internal pull-up. It can be
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
1.1.2 WDI
If WDI remains high or low for 1.6 sec, the internal watchdog timer runs out and reset is
triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a
rising or falling edge.
The watchdog function can be disabled by allowing the WDI pin to float.
1.1.3 RST
Pulses low for t
rec
when triggered, and stays low whenever V
CC
is below the reset threshold
or when MR
is a logic low. It remains low for t
rec
after either V
CC
rises above the reset
threshold, the watchdog triggers a reset, or MR
goes from low to high.
1.1.4 RST
Pulses high for t
rec
when triggered, and stays high whenever V
CC
is above the reset
threshold or when MR
is a logic high. It remains high for t
rec
after either V
CC
falls below the
reset threshold, the watchdog triggers a reset, or MR
goes from high to low.
1
PFO
PFI
MR
RST
V
CC
V
OUT
V
BAT
V
SS
AI07890
SO8/TSSOP8
2
3
4
8
7
6
5
1
E
CON
E
WDI
RST
V
CC
V
OUT
V
BAT
V
SS
AI07892
SO8/TSSOP8
2
3
4
8
7
6
5