Datasheet

STM690A/692A/703/704/802/805/817/818/819 Operation
Doc ID 10522 Rev 10 13/43
2 Operation
2.1 Reset output
The STM690A/692A/703/704/802/805/817/818/819 Supervisor asserts a reset signal to the
MCU whenever V
CC
goes below the reset threshold (V
RST)
, a watchdog time-out occurs, or
when the Push-button Reset Input (MR
) is taken low. RST is guaranteed to be a logic low
(logic high for STM805) for 0V < V
CC
< V
RST
if VBAT is greater than 1 V. Without a backup
battery, RST
is guaranteed valid down to V
CC
=1 V.
During power-up, once V
CC
exceeds the reset threshold an internal timer keeps RST low for
the reset time-out period, t
rec
. After this interval RST returns high.
If V
CC
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset time-out period (t
rec
). Any time V
CC
goes below the reset threshold
the internal timer clears. The reset timer starts when V
CC
returns above the reset threshold.
2.2 Push-button reset input (STM703/704/819)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t
rec
(see
Figure 41) after it returns high. The MR
input has an internal 40 kΩ pull-up resistor, allowing
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain/collector outputs. Connect a normally open momentary switch from MR
to GND
to create a manual reset function; external debounce circuitry is not required. If MR
is driven
from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor
from MR
to GND to provide additional noise immunity. MR may float, or be tied to V
CC
when
not used.
2.3 Watchdog input (NOT available on STM703/704/819)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within t
WD
(1.6 sec typ), the reset is asserted. The internal
watchdog timer is cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns.
If WDI is tied high or low, a reset pulse is triggered every 1.8 sec (t
WD
+ t
rec
).
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting (see Figure 42).
Note: 1 The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
2 Input pulses less than 20 ns will be ignored.