Datasheet

Operation STM705, STM706, STM707, STM708, STM813L
12/33 Doc ID 10520 Rev 9
3.4 Watchdog output (STM705/706/813L)
When V
CC
drops below the reset threshold, WDO will go low even if the watchdog timer has
not yet timed out. However, unlike the reset output, WDO
goes high as soon as V
CC
exceeds the reset threshold. WDO
may be used to generate a reset pulse by connecting it
to the MR
input.
3.5 Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the V
RST
comparator). If PFI is less than the power-fail threshold (V
PFI
), the power-fail
output (PFO
) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 9) to either the unregulated DC input (if it is available) or the regulated output of
the V
CC
regulator. The voltage divider can be set up such that the voltage at PFI falls below
V
PFI
several milliseconds before the regulated V
CC
input to the STM705/706/707/708/ 813L
or the microprocessor drops below the minimum operating voltage.
If the comparator is unused, PFI should be connected to V
SS
and PFO left unconnected.
PFO
may be connected to MR on the STM703/704/818 so that a low voltage on PFI will
generate a reset output.
3.6 Ensuring a valid reset output down to V
CC
= 0 V
When V
CC
falls below 1 V, the state of the RST output can no longer be guaranteed, and
becomes essentially an open circuit. If a high value pulldown resistor is added to the RST
pin, the output will be held low during this condition. A resistor value of approximately
100 kΩ will be large enough to not load the output under operating conditions, but still
sufficient to pull RST
to ground during this low voltage condition (see Figure 10).
Figure 10. Reset output valid to ground circuit
AI08835
STMXXX
RST
R1