Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Description
- Figure 1. Logic diagram (STM6821/6822/6823)
- Figure 2. Logic diagram (STM6321/6322/6824/6825)
- Table 2. Signal names
- Figure 3. STM6822/6823 SOT23-5 connections
- Figure 4. STM6821 SOT23-5 connections
- Figure 5. STM6322/6825 SOT23-5 connections
- Figure 6. STM6321/6824 SOT23-5 connections
- 1.1 Pin descriptions
- 2 Operation
- 3 Typical operating characteristics
- Figure 15. VCC-to-reset output delay vs. temperature
- Figure 16. Supply current vs. temperature
- Figure 17. MR-to-reset output delay vs. temperature
- Figure 18. Normalized power-up trec vs. temperature
- Figure 19. Normalized reset threshold voltage vs. temperature
- Figure 20. Normalized power-up watchdog timeout period
- Figure 21. Voltage output low vs. ISINK
- Figure 22. Voltage output high vs. ISOURCE
- Figure 23. Maximum transient duration vs. reset threshold overdrive
- 4 Maximum ratings
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Package mechanical data
- 8 Part numbering
- 9 Revision history

List of figures STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
4/31 Doc ID 11110 Rev 12
List of figures
Figure 1. Logic diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic diagram (STM6321/6322/6824/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. STM6822/6823 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. STM6821 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. STM6322/6825 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. STM6321/6824 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Block diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Block diagram (STM6321/6824) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. Block diagram (STM6322/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11. STM6321/6322/6822 open drain RST
output with multiple supplies . . . . . . . . . . . . . . . . . 10
Figure 12. Ensuring RST
valid to V
CC
= 0, (active low push-pull outputs) . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. Ensuring RST valid to V
CC
= 0, (active high, push-pull outputs) . . . . . . . . . . . . . . . . . . . . 12
Figure 14. Interfacing to microprocessors with bidirectional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15. V
CC
-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16. Supply current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17. MR
-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Normalized power-up t
rec
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Normalized reset threshold voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Normalized power-up watchdog timeout period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Voltage output low vs. I
SINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22. Voltage output high vs. I
SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 23. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 25. MR
timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 26. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 27. SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 25
Figure 28. Carrier tape for SOT23-5 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26