Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Description
- Figure 1. Logic diagram (STM6821/6822/6823)
- Figure 2. Logic diagram (STM6321/6322/6824/6825)
- Table 2. Signal names
- Figure 3. STM6822/6823 SOT23-5 connections
- Figure 4. STM6821 SOT23-5 connections
- Figure 5. STM6322/6825 SOT23-5 connections
- Figure 6. STM6321/6824 SOT23-5 connections
- 1.1 Pin descriptions
- 2 Operation
- 3 Typical operating characteristics
- Figure 15. VCC-to-reset output delay vs. temperature
- Figure 16. Supply current vs. temperature
- Figure 17. MR-to-reset output delay vs. temperature
- Figure 18. Normalized power-up trec vs. temperature
- Figure 19. Normalized reset threshold voltage vs. temperature
- Figure 20. Normalized power-up watchdog timeout period
- Figure 21. Voltage output low vs. ISINK
- Figure 22. Voltage output high vs. ISOURCE
- Figure 23. Maximum transient duration vs. reset threshold overdrive
- 4 Maximum ratings
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Package mechanical data
- 8 Part numbering
- 9 Revision history

Package mechanical data STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
22/31 Doc ID 11110 Rev 12
V
OH
Output high voltage (RST)
V
CC
≥ 2.7 V, I
SOURCE
= 500 µA,
Reset not asserted
0.8 V
CC
V
V
CC
≥ 4.5 V, I
SOURCE
= 800 µA
, Reset not asserted
0.8 V
CC
V
Output high voltage (RST)
V
CC
≥ 1.0 V, I
SOURCE
= 1 µA,
Reset asserted (0 °C to 85 °C)
0.8 V
CC
V
V
CC
≥ 1.5 V, I
SOURCE
= 100 µA,
Reset asserted
0.8 V
CC
V
V
CC
≥ 2.55 V, I
SOURCE
= 500 µA,
Reset asserted
0.8 V
CC
V
V
CC
≥ 4.25 V, I
SOURCE
= 800 µA,
Reset asserted
0.8 V
CC
V
Reset thresholds
V
RST
(5)
Reset threshold
STM6xxxL
25 °C 4.561 4.630 4.699 V
–40 to 85 °C 4.514 4.746 V
STM6xxxM
25 °C 4.314 4.390 4.446 V
–40 to 85 °C 4.270 4.490 V
STM6xxxT
25 °C 3.040 3.080 3.110 V
–40 to 85 °C 3.000 3.150 V
STM6xxxS
25 °C 2.890 2.930 2.960 V
–40 to 85 °C 2.857 3.000 V
STM6xxxR
25 °C 2.590 2.630 2.660 V
–40 to 85 °C 2.564 2.696 V
STM6xxxZ
25 °C 2.266 2.300 2.335 V
–40 to 85 °C 2.243 2.358 V
STM6xxxY
25 °C 1.970 2.000 2.030 V
–40 to 85 °C 1.950 2.050 V
Reset threshold hysteresis
L/M versions 10 mV
T/S/R/Z/Y versions 5 mV
V
CC
to RST delay
(V
RST
– V
CC
= 100 mV, V
CC
falling at 1 mV/µs)
20 µs
t
rec
(6)
Reset pulse width
A11.42ms
Blank 140 200 280 ms
J 240 360 480 ms
Table 6. DC and AC characteristic (continued)
Sym-
bol
Alter-
native
Description Test condition
(1)
Min. Typ. Max. Unit