Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Description
- Figure 1. Logic diagram (STM6821/6822/6823)
- Figure 2. Logic diagram (STM6321/6322/6824/6825)
- Table 2. Signal names
- Figure 3. STM6822/6823 SOT23-5 connections
- Figure 4. STM6821 SOT23-5 connections
- Figure 5. STM6322/6825 SOT23-5 connections
- Figure 6. STM6321/6824 SOT23-5 connections
- 1.1 Pin descriptions
- 2 Operation
- 3 Typical operating characteristics
- Figure 15. VCC-to-reset output delay vs. temperature
- Figure 16. Supply current vs. temperature
- Figure 17. MR-to-reset output delay vs. temperature
- Figure 18. Normalized power-up trec vs. temperature
- Figure 19. Normalized reset threshold voltage vs. temperature
- Figure 20. Normalized power-up watchdog timeout period
- Figure 21. Voltage output low vs. ISINK
- Figure 22. Voltage output high vs. ISOURCE
- Figure 23. Maximum transient duration vs. reset threshold overdrive
- 4 Maximum ratings
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Package mechanical data
- 8 Part numbering
- 9 Revision history
Operation STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
12/31 Doc ID 11110 Rev 12
Figure 12. Ensuring RST valid to V
CC
= 0, (active low push-pull outputs)
Figure 13. Ensuring RST valid to V
CC
= 0, (active high, push-pull outputs)
1. This configuration does not work on open drain outputs of the STM6321/6322/6822.
2.6 Interfacing to microprocessors with bidirectional reset pins
Microprocessors with bidirectional reset pins can contend with the STM6321
/
6322
/
6821
/
6822
/
6823
/
6824
/
6825 reset output. For example, if the reset output is driven high and the
microprocessor wants to pull it low, signal contention will result. To prevent this from
occurring, connect a 4.7 kΩ resistor between the reset output and the microprocessor’s
reset I/O as in Figure 14.
Figure 14. Interfacing to microprocessors with bidirectional reset I/O
AI09138
STM6XXX
RSTGND
V
CC
V
CC
R1
AI09139
STM6XXX
RST
GND
V
CC
V
CC
R1
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34-888
234
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234
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SYSTEMCOMPONENTS
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