Datasheet

Operation STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
10/31 Doc ID 11110 Rev 12
2 Operation
2.1 Reset output
The STM6xxx supervisor asserts a reset signal to the MCU whenever V
CC
goes below the
reset threshold (V
RST
), a watchdog timeout occurs, or when the push-button reset input
(MR
) is taken low. Reset is guaranteed valid for V
CC
< V
RST
down to V
CC
=1 V for
T
A
= 0 to 85 °C.
During power-up, once V
CC
exceeds the reset threshold an internal timer keeps reset low for
the reset timeout period, t
rec
. After this interval reset is de-asserted.
Each time RST
is asserted, it stays low for at least the reset timeout period (t
rec
). Any time
V
CC
goes below the reset threshold the internal timer clears. The reset timer starts when
V
CC
returns above the reset threshold.
2.2 Open drain RST output
The STM6321/6322/6822 have an active low, open drain reset output. This output structure
will sink current when RST
is asserted. Connect a pull-up resistor from RST to any supply
voltage up to 6 V (see Figure 11). Select a resistor value large enough to register a logic
low, and small enough to register a logic high while supplying all input current and leakage
paths connected to the reset output line. A 10 kΩ pull-up resistor is sufficient in most
applications.
Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies
1. STM6322/6822.
2. STM6321/6822.
3. STM6321/6322.
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