Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Description
- Figure 1. Logic diagram (STM6717/18)
- Figure 2. Logic diagram (STM6777/78)
- Figure 3. Logic diagram (STM6719/20)
- Figure 4. Logic diagram (STM6779/80)
- Table 2. Signal names
- Figure 5. STM6717/18 SOT23-5 connections
- Figure 6. STM6777/78 SOT23-6 connections
- Figure 7. STM6719/20 SOT23-6 connections
- Figure 8. STM6779/80 SOT23-6 connections
- 1.1 Pin descriptions
- 1.1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80
- 1.1.2 Active-low, open drain reset output (RST) - STM6717/19/77/79
- 1.1.3 Push-button reset input (MR)
- 1.1.4 Manual reset delay input (MRC) - STM6777/78/79/80)
- 1.1.5 Primary supply voltage monitoring input (VCC1)
- 1.1.6 Secondary supply voltage monitoring input (VCC2)
- 1.1.7 Adjustable reset comparator input (RSTIN; STM6719/20/79/80)
- 2 Operation
- 3 Typical operating characteristics
- Figure 13. Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V)
- Figure 14. Supply current vs. temperature (VCC1 = 3.6 V; VCC2 = 2.75 V)
- Figure 15. Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V)
- Figure 16. Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.0 V)
- Figure 17. Normalized VCC reset time-out period vs. temperature
- Figure 18. Maximum VCC transient duration vs. reset threshold overdrive
- Figure 19. Normalized VRST1 threshold vs. temperature
- Figure 20. Normalized VRST2 threshold vs. temperature
- Figure 21. Reset input threshold vs. temperature
- Figure 22. VCC1-to-reset delay vs. temperature
- Figure 23. Reset input-to-reset output delay vs. temperature
- Figure 24. MR-to-reset output delay vs. temperature (VCC1 = 3.6V)
- 4 Maximum rating
- 5 DC and AC parameters
- 6 Package mechanical data
- Figure 28. SOT23-5 - 5-lead small outline transistor package mechanical drawing
- Table 8. SOT23-5 - 5-lead small outline transistor package mechanical data
- Figure 29. SOT23-6 - 6-lead small outline transistor package mechanical drawing
- Table 9. SOT23-6 - 6-lead small outline transistor package mechanical data
- Figure 30. Carrier tape for SOT23-5L and SOT23-6L
- Table 10. Carrier tape dimensions for SOT23-5L and SOT23-6L
- 7 Part numbering
- 8 Revision history
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description
Doc ID 11469 Rev 8 5/30
1 Description
The STM6717/18/19/20 and STM6777/78/79/80 supervisors are a family of low-voltage/low-
supply current processor (micro or DSP) supervisors, designed to monitor two (or three)
system power supply voltages. They are targeted at applications such as set-top boxes
(STBs), portable, battery-powered systems, networking, and communication systems.
All device options have a push-button-type manual reset input (MR
). The
STM6777/78/79/80 also includes an option which enables the user to delay the start of the
manual reset process from 6 µs (MRC pin left open) or more with external capacitor. The
delay is implemented by connecting the appropriately sized capacitor between the MRC pin
and V
SS
(typical 4 s delay with a 3.3 µF capacitor, see Table 7 on page 21).
Two of the three supplies monitored (V
CC1
and V
CC2
) have fixed (customer-selectable,
factory-trimmed) thresholds (V
RST1
and V
RST2
). The third voltage is monitored using an
externally adjustable RSTIN threshold (0.626 V internal reference).
If any of the three monitored voltages drop below its factory-trimmed or adjustable
thresholds, or if MR
is asserted to logic low, a RST is asserted (driven low). Once asserted,
RST
is maintained at low for a minimum delay period (t
rec
) after ALL supplies rise above
their respective thresholds and MR
returns to high. These devices are guaranteed to be in
the correct reset output logic state when V
CC1
and/or V
CC2
is greater than 0.8 V.
These devices are available in standard 5-pin or 6-pin SOT23 packages (see Ta bl e 1 o n
page 1).