Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Description
- Figure 1. Logic diagram (STM6717/18)
- Figure 2. Logic diagram (STM6777/78)
- Figure 3. Logic diagram (STM6719/20)
- Figure 4. Logic diagram (STM6779/80)
- Table 2. Signal names
- Figure 5. STM6717/18 SOT23-5 connections
- Figure 6. STM6777/78 SOT23-6 connections
- Figure 7. STM6719/20 SOT23-6 connections
- Figure 8. STM6779/80 SOT23-6 connections
- 1.1 Pin descriptions
- 1.1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80
- 1.1.2 Active-low, open drain reset output (RST) - STM6717/19/77/79
- 1.1.3 Push-button reset input (MR)
- 1.1.4 Manual reset delay input (MRC) - STM6777/78/79/80)
- 1.1.5 Primary supply voltage monitoring input (VCC1)
- 1.1.6 Secondary supply voltage monitoring input (VCC2)
- 1.1.7 Adjustable reset comparator input (RSTIN; STM6719/20/79/80)
- 2 Operation
- 3 Typical operating characteristics
- Figure 13. Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V)
- Figure 14. Supply current vs. temperature (VCC1 = 3.6 V; VCC2 = 2.75 V)
- Figure 15. Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V)
- Figure 16. Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.0 V)
- Figure 17. Normalized VCC reset time-out period vs. temperature
- Figure 18. Maximum VCC transient duration vs. reset threshold overdrive
- Figure 19. Normalized VRST1 threshold vs. temperature
- Figure 20. Normalized VRST2 threshold vs. temperature
- Figure 21. Reset input threshold vs. temperature
- Figure 22. VCC1-to-reset delay vs. temperature
- Figure 23. Reset input-to-reset output delay vs. temperature
- Figure 24. MR-to-reset output delay vs. temperature (VCC1 = 3.6V)
- 4 Maximum rating
- 5 DC and AC parameters
- 6 Package mechanical data
- Figure 28. SOT23-5 - 5-lead small outline transistor package mechanical drawing
- Table 8. SOT23-5 - 5-lead small outline transistor package mechanical data
- Figure 29. SOT23-6 - 6-lead small outline transistor package mechanical drawing
- Table 9. SOT23-6 - 6-lead small outline transistor package mechanical data
- Figure 30. Carrier tape for SOT23-5L and SOT23-6L
- Table 10. Carrier tape dimensions for SOT23-5L and SOT23-6L
- 7 Part numbering
- 8 Revision history
STM6717/6718/6719/6720/STM6777/6778/6779/6780 DC and AC parameters
Doc ID 11469 Rev 8 19/30
Table 6. DC and AC characteristics
Sym
Alter-
native
Description Test condition
(1)
Min Typ Max Unit
V
CC
Operating voltage 0.8 5.5 V
I
CC1
V
CC1
supply current
V
CC1
< 5.5 V, all I/O pins open 12 35 µA
V
CC1
< 3.6 V, all I/O pins open 8 23 µA
I
CC2
V
CC2
supply current
V
CC2
< 3.6 V, all I/O pins open 3 9 µA
V
CC2
< 2.75 V, all I/O pins open 2.5 7 µA
I
LI
(2)
Input leakage current 0 V = V
IN
= V
CC
–1 +1 µA
I
LO
Open drain RST output
leakage current
V
CC1
> V
RST1
, V
CC2
> V
RST2
;
RST
not asserted
0.5 µA
V
OL
Output low voltage (RST;
push-pull or open drain)
V
CC1
or V
CC2
≥ 0.8 V,
I
SINK
= 1 µA, RST asserted
0.3 V
V
CC1
or V
CC2
≥ 1.0 V,
I
SINK
= 50 µA, RST asserted
0.3 V
V
CC1
or V
CC2
≥ 1.2 V,
I
SINK
= 100 µA, RST asserted
0.3 V
V
CC1
or V
CC2
≥ 2.7 V,
I
SINK
= 1.2 mA, RST asserted
0.3 V
V
CC1
or V
CC2
≥ 4.5 V,
I
SINK
= 3.2 mA, RST asserted
0.4 V
V
OH
Output high voltage (RST;
push-pull only)
V
CC1
≥ 1.8 V, I
SOURCE
= 200 µA,
RST
not asserted
0.8V
CC1
V
V
CC1
≥ 2.7 V, I
SOURCE
= 500 µA,
RST not asserted
0.8V
CC1
V
V
CC1
≥ 4.5 V, I
SOURCE
= 800 µA,
RST not asserted
0.8V
CC1
V
t
R
(3)
Push-pull RST rise time
(STM6718/20/78/80)
Rise time measured from 10% to
90% of V
CC
;
C
L
= 5 pF, V
CC
= 3.3 V
525ns
Reset thresholds
V
RST
(4)
V
TH1
V
CC1
reset threshold
L (falling) 4.500 4.625 4.750 V
M (falling) 4.250 4.375 4.500 V
T (falling) 3.000 3.075 3.150 V
S (falling) 2.850 2.925 3.000 V
R (falling) 2.550 2.625 2.700 V
Z (falling) 2.250 2.313 2.375 V
Y (falling) 2.125 2.188 2.250 V
W (falling) 1.620 1.665 1.710 V
V (falling) 1.530 1.575 1.620 V