STM6717/6718/6719/6720 STM6777/6778/6779/6780 Dual/triple ultra-low voltage supervisors with push-button reset (with delay option) Features ■ Primary supply (VCC1) monitor. Fixed (factory-programmed) reset thresholds: 4.63 V to 1.58 V ■ Secondary supply (VCC2) monitor (STM6717/18/19/20/77/78) ■ Fixed (factory-programmed) reset thresholds: 3.08 V to 0.79 V ■ Tertiary supply monitor (using externally adjustable RSTIN): 0.
Contents STM6717/6718/6719/6720/STM6777/6778/6779/6780 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80 . . . . . . . . 7 1.1.2 Active-low, open drain reset output (RST) - STM6717/19/77/79 . . . . . . . 7 1.1.3 Push-button reset input (MR) . . . .
STM6717/6718/6719/6720/STM6777/6778/6779/6780 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin functions . . . . . . . . . . . . . . .
List of figures STM6717/6718/6719/6720/STM6777/6778/6779/6780 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. 4/30 Logic diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STM6717/6718/6719/6720/STM6777/6778/6779/6780 1 Description Description The STM6717/18/19/20 and STM6777/78/79/80 supervisors are a family of low-voltage/lowsupply current processor (micro or DSP) supervisors, designed to monitor two (or three) system power supply voltages. They are targeted at applications such as set-top boxes (STBs), portable, battery-powered systems, networking, and communication systems. All device options have a push-button-type manual reset input (MR).
Description Figure 1. STM6717/6718/6719/6720/STM6777/6778/6779/6780 Logic diagram (STM6717/18) Figure 2. Logic diagram (STM6777/78) VCC2 VCC1 VCC2 VCC1 MRC MR STM6717 STM6718 STM6777 STM6778 RST MR VSS RST VSS AI10413 Figure 3. Logic diagram (STM6719/20) AI10415 Figure 4. Logic diagram (STM6779/80) VCC VCC2 VCC1 RSTIN RSTIN MR STM6719 STM6720 MRC RST STM6779 STM6780 RST MR VSS VSS AI10414 Table 2.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 5. STM6717/18 SOT23-5 connections RST 1 VSS 2 MR 3 5 4 Figure 6. VCC1 VCC2 Description STM6777/78 SOT23-6 connections RST 1 6 VCC1 VSS 2 5 MRC MR 3 4 VCC2 AI10417 Figure 7. STM6719/20 SOT23-6 connections AI10418 Figure 8. STM6779/80 SOT23-6 connections RST 1 6 VCC1 RST 1 6 VCC1 VSS 2 5 RSTIN VSS 2 5 RSTIN MR 3 4 VCC2 MR 3 4 MRC AI10419 1.1 Pin descriptions 1.1.
Description STM6717/6718/6719/6720/STM6777/6778/6779/6780 VCC1. It can be driven from a TTL or CMOS logic line, or with open drain/collector outputs, or connected to VSS through a switch. If unused, leave this pin open or connect it to VCC1. Connect a normally open momentary switch from MR to VSS; external debounce circuitry is not required. (If MR is driven from long cables or if the device is used in noisy environments, connecting a 0.1µF capacitor from MR to VSS provides additional noise immunity. 1.1.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 9. Description Block diagram VCC1 VCC2 VRST1 COMPARE VRST2 COMPARE VREF/2 = 0.626 COMPARE (1) RSTIN(2) VCC1 trec Generator RST Logic MR MRC(3) AI10421 1. VCC2 input is available on STM6717/18/19/20/77/78. 2. RSTIN available only on STM6719/20/79/80. 3. MRC available only on STM6777/78/79/80. Figure 10. Hardware hookup From DC/DC Converter VCC2(1) VCC1 VCC1 VCC3 = (626.5mV) R1 + R2 R2 ( ) 0.1µF STM67xx VCC2 VCC3 0.
Operation STM6717/6718/6719/6720/STM6777/6778/6779/6780 2 Operation 2.1 Applications information 1. Interfacing to processors with bi-directional reset pins Most processors with bi-directional reset pins can interface directly to the open drain RST outputs (STM6717/19/77/79). Systems simultaneously requiring a push-pull RST output and a bi-directional reset interface can be in logic contention. To prevent this contention, connect a 4.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics 3 Typical operating characteristics Note: Typical values are at TA = 25 °C unless otherwise noted. Figure 13. Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V) 18 Supply current (µA) 16 14 12 10 ITOTAL ICC1 8 6 4 ICC2 2 0 –40 –20 0 20 40 60 80 Temperature (°C) AI11843 Figure 14. Supply current vs. temperature (VCC1 = 3.6 V; VCC2 = 2.
Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 15. Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V) 18 Supply current (µA) 16 14 12 10 8 ITOTAL 6 ICC1 4 2 ICC2 0 –40 –20 0 20 40 60 80 Temperature (°C) AI11845 Figure 16. Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics Figure 17. Normalized VCC reset time-out period vs. temperature 1.07 Reset period 1.05 1.03 1.01 0.99 0.97 –40 –20 0 20 40 60 80 Temperature (°C) AI11847 Maximum VCC transient duration (µs) Figure 18. Maximum VCC transient duration vs.
Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 19. Normalized VRST1 threshold vs. temperature VRST1 reset threshold 1.004 1.002 1.000 0.998 0.996 –40 –20 0 20 40 60 80 Temperature (°C) AI11849 Figure 20. Normalized VRST2 threshold vs. temperature VRST2 reset threshold 1.004 1.002 1.000 0.998 0.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics Figure 21. Reset input threshold vs. temperature Reset input threshold (mV) 630 629 628 627 626 625 624 –40 –20 0 20 40 60 80 Temperature (°C) AI11851 Figure 22. VCC1-to-reset delay vs.
Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 23. Reset input-to-reset output delay vs. temperature RSTIN-to-reset output delay (µs) 29.0 28.5 28.0 27.5 27.0 26.5 26.0 25.5 25.0 –40 –20 0 20 40 60 80 Temperature (°C) AI11853 Figure 24. MR-to-reset output delay vs. temperature (VCC1 = 3.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 4 Maximum rating Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
DC and AC parameters 5 STM6717/6718/6719/6720/STM6777/6778/6779/6780 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 5: Operating and AC measurement conditions.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Table 6. Sym DC and AC characteristics Alternative Description VCC Operating voltage ICC1 VCC1 supply current ICC2 VCC2 supply current ILI DC and AC parameters (2) ILO 0.8 Max Unit 5.5 V VCC1 < 5.5 V, all I/O pins open 12 35 µA VCC1 < 3.6 V, all I/O pins open 8 23 µA VCC2 < 3.6 V, all I/O pins open 3 9 µA VCC2 < 2.75 V, all I/O pins open 2.
DC and AC parameters Table 6. Sym VRST2 (4) DC and AC characteristics (continued) Alternative VTH2 Description tRD VCC to RST delay tRP Test condition(1) Min T (falling) 3.000 3.075 3.150 V S (falling) 2.850 2.925 3.000 V R (falling) 2.550 2.625 2.700 V Z (falling) 2.250 2.313 2.375 V Y (falling) 2.125 2.188 2.250 V W (falling) 1.620 1.665 1.710 V V (falling) 1.530 1.575 1.620 V I (falling) 1.350 1.388 1.425 V H (falling) 1.275 1.313 1.350 V G (falling) 1.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Table 6. Sym DC and AC parameters DC and AC characteristics (continued) Alternative Description Test condition(1) Min Typ Max Unit 0.3VC V Manual (push-button) reset input VIL MR input voltage C1 VIH MR minimum pulse width (STM6717/18/19/20) tMLMH tMLRL tMR tMRD MR minimum pulse width (STM6777/78/79/80) 0.
Package mechanical data 6 STM6717/6718/6719/6720/STM6777/6778/6779/6780 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Package mechanical data Figure 28. SOT23-5 – 5-lead small outline transistor package mechanical drawing E A1 1 e e1 D 5x b 5x 0.20 M CAB C 0.10 A A2 C A Datum A 0.20 θ C L B E1 Note: 0133778 Drawing is not to scale. Table 8. SOT23-5 – 5-lead small outline transistor package mechanical data mm inches Symb Min Typ Max Min Typ Max A — — 1.45 — — 0.057 A1 — — 0.15 — — 0.006 A2 0.90 1.15 1.30 0.035 0.045 0.
Package mechanical data STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 29. SOT23-6 – 6-lead small outline transistor package mechanical drawing E A1 1 e e1 D 6x b 0.10 6x M CAB C 0.10 A A2 C A Datum A 0.20 θ C L B E1 7049714 Note: Drawing is not to scale. Table 9. SOT23-6 – 6-lead small outline transistor package mechanical data mm inches Symb Min Typ Max Min Typ Max A — — 1.45 — — 0.057 A1 — — 0.15 — — 0.006 A2 0.90 1.15 1.30 0.035 0.045 0.051 b 0.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Package mechanical data Figure 30. Carrier tape for SOT23-5L and SOT23-6L P0 E P2 D T A0 F TOP COVER TAPE W B0 P1 CENTER LINES OF CAVITY K0 USER DIRECTION OF FEED AM03073v1 Note: Part pin 1 indicator is on bottom left for shipping method “F” and is on top right for shipping method “R” see Section 7. Table 10. Carrier tape dimensions for SOT23-5L and SOT23-6L Package W D 8.00 1.50 SOT23-5 +0.30/ +0.10/ SOT23-6 –0.10 –0.00 E P0 P2 F 1.
Part numbering STM6717/6718/6719/6720/STM6777/6778/6779/6780 7 Part numbering Table 11. Ordering information scheme Example: Device type STM67xx STM67xx LT WY 6 F Reset thresholds (VRST1 and VRST2) for VCC1 and VCC2 STM6717/18/19/20/77/78 (VRST1 and VRST2) STM6779/80 (VRST1 only) VRST2 Suffix VRST1 Suffix VRST1 LT 4.625 3.075 L–(1) 4.625 3.075 MS 4.375 2.925 T–(1) 2.925 MR 4.375 2.625 S–(1) 3.075 2.313 Y–(1) 2.188 TZ(1) TW(1) 3.075 1.665 V–(1) 1.575 TI 3.075 1.388 R– 2.625 3.075 1.110 Z– 2.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Table 12. Part numbering Marking description Part number VRST1 threshold (V) VRST2 threshold (V) Topside marking Bottomside marking STM6717SD 2.925 0.788 7SD1 PYWW STM6717SJ 2.925 0.875 7SJ1 PYWW STM6717SF 2.925 1.050 7SF1 PYWW STM6717TG 3.075 1.110 7TG1 PYWW STM6717TGG 3.075 1.110 7TG9 PYWW STM6717TW 3.075 1.665 7TW1 PYWW STM6717SV 2.925 1.575 7SV1 PYWW STM6717SY 2.925 2.188 7SY1 PYWW STM6717TZ 3.075 2.
Part numbering Table 12. STM6717/6718/6719/6720/STM6777/6778/6779/6780 Marking description (continued) Part number VRST1 threshold (V) VRST2 threshold (V) Topside marking Bottomside marking STM6778SF 2.925 1.050 7SF6 PYWW STM6778TG 3.075 1.110 7TG6 PYWW STM6778TW 3.075 1.665 7TW6 PYWW STM6778SV 2.925 1.575 7SV6 PYWW STM6778SY 2.925 2.188 7SY6 PYWW STM6778TZ 3.075 2.313 7TZ6 PYWW STM6779L 4.625 — 7Lx7 PYWW STM6779T 3.075 — 7Tx7 PYWW STM6779S 2.
STM6717/6718/6719/6720/STM6777/6778/6779/6780 8 Revision history Revision history Table 13. Document revision history Date Revision Changes 18-Oct-2004 1 25-Oct-2004 1.1 Descriptive text, sales types (Table 11) 14-Jan-2005 1.2 Update characteristics, pin functions (Table 2) 09-Feb-2005 1.3 Update characteristics (Figure 9; Table 3) 08-Apr-2005 1.4 Update characteristics and mechanical dimensions; add table (Figure 9, 10, 27, 28, 29; Table 4, 6, 11, 8, 9) 28-Jul-2005 1.
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