Datasheet

STM6600, STM6601 DC and AC characteristics
Doc ID 15453 Rev 11 41/52
C
SRD
I
SRD
C
SRD
charging current 100 150 200 nA
V
SRD
C
SRD
voltage threshold
V
CC
= 3.6 V, load on V
REF
pin
100 kΩ and mandatory 1 µF
capacitor, T
A
= 25 °C
1.5 V
t
SRD
Additional Smart Reset
delay time
External C
SRD
connected 10 s/µF
EN, EN
V
OL
Output low voltage
V
CC
= 2 V, I
SINK
= 1 mA,
enable asserted
0.3 V
V
OH
(5)
Output high voltage
V
CC
= 2 V, I
SOURCE
= 1 mA,
enable asserted
V
CC
– 0.3 V
t
EN_OFF
(6)
enable off to enable on V
CC
2.0 V406488ms
EN, EN
leakage current V
EN
= 2 V, enable open drain –0.1 +0.1 µA
RST
V
OL
Output low voltage
V
CC
= 2 V, I
SINK
= 1 mA,
RST
asserted
0.3 V
t
REC
RST pulse width V
CC
2.0 V 240 360 480 ms
RST
leakage current V
RST
= 3V –0.1 +0.1 µA
INT
V
OL
Output low voltage
V
CC
= 2 V, I
SINK
= 1 mA,
INT
asserted
0.3 V
t
INT_Min
Minimum INT pulse width V
CC
2.0 V203244ms
INT
leakage current V
INT
= 3 V –0.1 +0.1 µA
V
REF
V
REF
1.5 V voltage reference
V
CC
= 3.6 V, load on V
REF
pin
100 kΩ and mandatory 1 µF
capacitor, T
A
= 25 °C
1.485
–1%
1.5
1.515
+1%
V
1. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 1.6 V to 5.5 V (except where noted).
2. Typical values are at T
A
= +25 °C.
3. This blanking time allows the processor to start up correctly (see Figure 7, 8, 9, 10, 11, 12).
4. The internal pull-up resistor connected to the SR
input is optional (see Table 10 for detailed device options).
5. Valid for push-pull only.
6. Minimum delay time between enable deassertion and enable reassertion, allowing the application to complete the power-down
properly. PB
is ignored during this period.
Table 5. DC and AC characteristics (continued)
Symbol Parameter Test condition
(1)
Min. Typ.
(2)
Max. Unit