Datasheet

Operation STM6600, STM6601
12/52 Doc ID 15453 Rev 11
3 Operation
The STM6600-STM6601 simplified smart push-button on/off controller with Smart Reset
™
and power-on lockout enables and disables power for the application depending on push-
button states, signals from the processor, and battery voltage.
Power-on
Because most of the processors have outputs in high-Z state before initialization, an internal
pull-down resistor is connected to PS
HOLD
input during startup (see Figure 7, 8, 9, 10, 11,
12, 13, and 18).
To power up the device the push-button PB
has to be pressed for at least t
DEBOUNCE
and
V
CC
has to be above V
TH+
for the whole t
DEBOUNCE
period. If the battery voltage drops
below V
TH+
during the t
DEBOUNCE
, the counter is reset and starts to count again when V
CC
>
V
TH+
(see Figure 13). After t
DEBOUNCE
the enable signal is asserted (EN goes high, EN
goes low), reset output RST
is asserted for t
REC
and then the startup routine is performed
by the processor. During initialization, the processor sets the PS
HOLD
signal high.
On the STM6600 the PS
HOLD
signal has to be set high prior to push-button release and
t
ON_BLANK
expiration, otherwise the enable signal is deasserted (EN goes low, EN goes
high) - see Figure 7, 8, 9, and 10. The time up to push-button release represents the
maximum time allowed for the system to power up and initialize the circuits driving the
PS
HOLD
input. If the PS
HOLD
signal is low at push-button release, the enable output is
deasserted immediately, thus turning off the system power. If t
ON_BLANK
expires prior to
push-button release, the PS
HOLD
state is checked at its expiration. This safety feature
disables the power and prevents discharging the battery if the push-button is stuck or it is
held for an unreasonable period of time and the application is not responding (see Figure 8
and 10). PB
status, INT status and V
CC
undervoltage detection are not monitored until
power-up is completed.
On the STM6601 the PS
HOLD
signal has to be set high before t
ON_BLANK
expires, otherwise
the enable signal is deasserted - see Figure 11 and 12. In this case the t
ON_BLANK
period is
the maximum time allowed for the power switch and processor to perform the proper power-
on. If the PS
HOLD
signal is low at the end of the blanking period, the enable output is
released immediately, thus turning off the system power. PB
status, INT status and V
CC
undervoltage detection are not monitored during the entire t
ON_BLANK
period. This failsafe
feature prevents the user from turning on the system when there is a faulty power switch or
an unresponsive microprocessor.
Push-button interrupt
If the device works under normal operation (i.e. PS
HOLD
is high) and the push-button PB is
pressed for more than t
DEBOUNCE
, a negative pulse with minimum t
INT
_
Min
width is
generated on the INT
output. By connecting INT to the processor interrupt input (INT or
NMI
) a safeguard routine can be performed and the power can be shut down by setting
PS
HOLD
low - see Figure 14.
Forced power-down mode
The PS
HOLD
output can be forced low anytime during normal operation by the processor
and can deassert the enable signal - see Figure 14.
Undervoltage detection
If V
CC
voltage drops below V
TH-
voltage threshold during normal operation, the INT output is
driven low (see Figure 20 and Figure 21).