Datasheet

STM6600, STM6601 Pin descriptions
Doc ID 15453 Rev 11 9/52
2 Pin descriptions
V
CC
- power supply input
V
CC
is monitored during startup and normal operation for sufficient voltage level. Decouple
the V
CC
pin from ground by placing a 0.1 µF capacitor as close to the device as possible.
SR
- Smart Reset
™
button input
This input is equipped with voltage detector with a factory-trimmed threshold and has ±8 kV
HBM ESD protection.
Both PB
and SR buttons have to be pressed and held for t
SRD
period so the long push is
recognized and the reset is asserted (or the enable output is deasserted depending on the
option) - see Figure 15, 16, and 17.
Active low SR
input is usually connected to GND through the momentary push-button (see
Figure 1) and it has an optional 100 kΩ pull-up resistor. It is also possible to drive this input
using an external device with either open drain (recommended) or push-pull output. Open
drain output can be connected in parallel with push-button or other open drain outputs,
which is not possible with push-pull output. S
R input is monitored for falling edge after
power-up and must not be grounded permanently.
V
REF
- external precise 1.5 V voltage reference
This 1.5 V voltage reference is specified with very tight accuracy of 1% (see Table 5). It has
proper output voltage as soon as the reset output is deasserted (i.e. after t
REC
expires) and
it is disabled when the device enters standby mode. A mandatory capacitor needs to be
connected to V
REF
output (even if V
REF
is not used). Capacitor value of 1 µF is
recommended.
PS
HOLD
input
This input is equipped with a voltage detector with a factory-trimmed threshold. It is used to
confirm correct power-up of the device (if EN or EN
is not asserted) or to initiate a shutdown
(if EN or EN
is asserted).
Forcing PS
HOLD
high during power-up confirms the proper start of the application and keeps
enable output asserted. Because most processors have outputs in high-Z state before
initialization, an internal pull-down resistor is connected to PS
HOLD
input during startup (see
Figure 7, 8, 9, 10, 11, 12, 13, and 18).
Forcing the PS
HOLD
signal low during normal operation deasserts the enable output (see
Figure 14). Input voltage on this pin is compared to an accurate voltage reference.
C
SRD
- Smart Reset
™
delay time input
A capacitor to ground determines the additional time (t
SRD
) that PB with SR must be
pressed and held before a long push is recognized. The connected C
SRD
capacitor is
charged with I
SRD
current. Additional Smart Reset
™
delay time t
SRD
ends when voltage on
the C
SRD
capacitor reaches the V
SRD
voltage threshold. It is recommended to use a low
ESR capacitor (e.g. ceramic). If the capacitor is not used, leave the C
SRD
pin open. If no
capacitor is connected, there is no t
SRD
and a long push is recognized right after t
INT_Min
expires (see Figure 18 and 19).