STM6524 6-pin Smart Reset™ Datasheet − production data Features ■ Operating voltage 1.65 V to 5.5 V ■ Low supply current 1.5 µA ■ Integrated test mode ■ Dual Smart Reset™ push-button inputs with fixed extended reset setup delay (tSRC) from 0.5 s to 10 s in 0.5 s steps (typ.
Contents STM6524 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Ground (VSS) . . .
STM6524 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of figures STM6524 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. 4/24 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . .
STM6524 1 Description Description The Smart Reset™ devices provide a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing extended Smart Reset™ input delay time (tSRC) and combined push-button inputs, which together ensures a safe reset and eliminates the need for a specific dedicated reset button.
Description STM6524 Figure 1. Logic diagram 6## 32 34- 234 32 '.$ !- Figure 2. Pin connections (top view) 633 32 234 34 6## 32 .
STM6524 Table 1. Pin Name 1 VSS 2 SR1 Description Signal names Type Supply ground Ground Input 3 RST Output 4 NC - 5 SR0 Input 6 VCC Figure 3. Description Secondary push-button Smart Reset™ input. Active low. Optional pull-up resistor. Reset output (open drain with optional pull-up resistor, active low) (push-pull – active low or active high) Not connected (not bonded; should be connected to VSS) Primary push-button Smart Reset™ input. Active low. Optional pull-up resistor.
Pin descriptions STM6524 2 Pin descriptions 2.1 Power supply (VCC) This pin is used to provide power to the Smart Reset™ device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the VCC and VSS pins, as close to the STM6524 device as possible. 2.2 Ground (VSS) Ground pin for the device. 2.3 Smart Reset™ input (SR0) Push-button Smart Reset™ input is active low with optional pull-up resistor.
STM6524 3 Typical application diagram Typical application diagram Figure 4. Single-button Smart Reset™ typical hookup 6## 6## 6## 234 2%3%4 34- -#5 32 ).4 .-) 32 633 633 053( "544/. 37)4#( !- 6 1. External pull-up resistor requested if the reset output (RST) is open drain type without internal pull-up. 2. External pull-up resistor requested if the Smart Reset™ inputs (SR0 and SR1) have no internal pull-up. 3.
Typical application diagram Figure 5. STM6524 Dual-button Smart Reset™ typical hookup 6## 6## 6## 234 2%3%4 34- -#5 32 32 ).4 .-) 633 633 053( "544/. 37)4#( 053( "544/. 37)4#( !- 6 1. External pull-up resistor requested if the reset output (RST) is open drain type without internal pull-up. 2. External pull-up resistor requested if the Smart Reset™ inputs (SR0 and SR1) have no internal pull-up.
STM6524 Timing waveforms 4 Timing waveforms Figure 6. Option without tREC 6 6## 6 6 6 3TART TIMER %ND TIMER 0USH BUTTON CONTROLLED OUTPUT T32# 32 'LITCH IMMUNITY 32 234 !- 6 Figure 7.
Timing waveforms Figure 8. STM6524 Undervoltage condition 6 6## 6 6 6 32 6 6 32 6 6 234 6 T32# 4IME S !- 1. If undervoltage occurs (VCC drops below 1.575 V typ.) while reset output is active, the reset output is released and goes inactive.
STM6524 Typical operating characteristics Figure 9. Supply current (ICC) vs. temperature (TA) 3UPPLY CURRENT )## ! 6## 6 6## 6 6## 6 4EMPERATURE # !- 6 Figure 10. Smart Reset™ delay (tSRC) vs. temperature (TA), tSRC = 7.5 s (typ.
Typical operating characteristics STM6524 Figure 11. Test mode entry voltage (VTEST) vs. temperature (TA) 4EST MODE ENTRY VOLTAGE 64%34 6 6## 6 6## 6 6## 6 4EMPERATURE 4! # !- Figure 12. Initial test mode time (tSRC-INI) vs. temperature (TA) )NITIAL TEST MODE TIME T32#?).
STM6524 6 Maximum ratings Maximum ratings Stressing the device above the rating listed in Table 2: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in Table 3: Operating and measurement conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC and AC parameters 7 STM6524 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters inTable 4: DC and AC characteristic that follow, are derived from tests performed under the measurement conditions summarized in Table 3: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 3.
STM6524 Table 4. DC and AC parameters DC and AC characteristic Symbol Parameter VCC Supply voltage(3) ICC Supply current (inputs in their inactive state, tSRC counter is not running) VOL VOH tREC Reset output voltage low Reset output voltage high (push-pull output only) Reset timeout delay, factory-programmed Test conditions(1) Min. Typ.(2) 1.65 Max. Unit 5.5 V VCC = 3.0 V 1.1 2.5 µA VCC = 5.0 V 1.5 3.0 µA VCC ≥ 4.5 V, sinking 3.2 mA 0.3 V VCC ≥ 3.3 V, sinking 2.5 mA 0.
Package information 8 STM6524 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. Package outline for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch $ ! " 0). ).$%8 !2%! $ X% % # X # X 4/0 6)%7 # # ! X 3%!4). ' 0,!.
STM6524 Package information Table 5. Mechanical data for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch Dimensions Symbol Drawing (millimeters) Drawing (inches) Note Min. Typ. Max. Min. Typ. Max. A 0.50 0.55 0.60 0.020 0.022 0.024 A1 0.00 0.02 0.05 0.0000 0.0008 0.0020 b 0.15 0.20 0.25 0.006 0.008 0.010 D 1.30 BSC 0.051 BSC E 1.60 BSC 0.063 BSC e 0.40 BSC 0.016 BSC L 0.250 N 0.325 0.400 0.0098 6 0.0128 0.0157 6 Figure 14. Footprint recommendation for UDFN6 1.
Package information STM6524 Figure 15. Carrier tape for UDFN6 1.6 x 1.3 x 0.55 mm 0 4 0O % 9 $ #, & 7 2%& "O 9 0 !O +O 3%#4)/. 9 9 !O "O +O & 0 7 !- 1. Measured from centreline of sprocket hole to centreline of pocket. 2. Cumulative tolerance of 10 sprocket holes is ± 0.20. 3. Measured from centreline of sprocket hole to centreline of pocket.
STM6524 9 Part numbering Part numbering Table 6. Ordering information scheme Example: STM6524 A H A R DL 6 F Device type STM6524 Reset (VCC monitoring threshold) voltage VRST A = no VCC monitoring feature Smart Reset™ set up delay (tSRC)(1) H = factory programmable tSRC = 4.0 s, no pull-up L = factory programmable tSRC = 6.0 s, no pull-up P = factory programmable tSRC = 7.5 s, no pull-up U = factory programmable tSRC = 10.
Package marking information 10 STM6524 Package marking information Table 7. Package marking Part number tSRC (s) Smart Reset™ inputs(1) Output type(2) tREC option (ms)(3) STM6524AHARDL6F 4.0 AL OD, AL No tREC UDFN6 HA STM6524ALABDL6F 6.0 AL OD, AL 360 UDFN6 LC STM6524ALARDL6F 6.0 AL OD, AL No tREC UDFN6 LA STM6524APARDL6F 7.5 AL OD, AL No tREC UDFN6 PA STM6524AUABDL6F 10.0 AL OD, AL 360 UDFN6 UC STM6524AUARDL6F 10.
STM6524 11 Revision history Revision history Table 8. Document revision history Date Revision Changes 07-Oct-2011 1 Initial release. 13-Jun-2012 2 Updated Features, Section : Test mode, Table 4, title of Section 8, minor text corrections throughout document. 31-Aug-2012 3 Updated Table 7 (added “(ms)” to tREC option, added STM6524ALABDL6F and STM6524AUABDL6F devices).
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