Datasheet

STM6519 Timing diagrams
Doc ID 022111 Rev 6 11/25
5 Timing diagrams
Figure 8. RST output without t
REC
option
1. V
CC
should be powered up before or together with voltage on the SR input to prevent entering test mode by creating
a condition V(SR) > V
CC
+1.1 V typ.
Figure 9. RST output with t
REC
option
1. V
CC
should be powered up before or together with voltage on the SR input to prevent entering test mode by creating
a condition V(SR
) > V
CC
+1.1 V typ.