STM6519 4-pin Smart Reset™ Datasheet - production data Features ■ Operating voltage range 2 V to 5.5 V ■ Low supply current 1 μA ■ Integrated test mode ■ Single Smart Reset™ push-button input with fixed extended reset setup delay (tSRC) from 0.5 s to 10 s in 0.5 s steps (typ.
Contents STM6519 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Device overview .
STM6519 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of figures STM6519 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. 4/25 STM6519 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 UDFN4 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STM6519 1 Description Description The Smart ResetTM devices provide a useful feature which ensures that inadvertent short reset push-button closures do not cause system resets. This is done by implementing an extended Smart Reset input delay time (tSRC), which ensures a safe reset and eliminates the need for a specific dedicated reset button. This reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset.
Description 1.2 STM6519 Logic diagram Figure 1. STM6519 logic diagram 6## 34- 32 234 '.$ !- 1.3 Pin connections Figure 2. UDFN4 pin connections (top view) 633 32 34 234 6## 5$&. !- Figure 3. UDFN6 pin connections (top view) 234 633 32 34 .# .# 6## 5$&. !- 6 1. Not connected (not bonded); should be connected to VSS.
STM6519 Device overview 2 Device overview Table 1. Signal names Pin number Name Type 4 RST Output 2 1 VSS Supply ground 3 2 SR Input 4 3 VCC Supply voltage 5 - NC - Not connected (not bonded); should be connected to VSS. 6 - NC - Not connected (not bonded); should be connected to VSS. UDFN6 UDFN4 1 Figure 4. Description Reset output, active-low, open drain. Ground Smart Reset input, active-low. Positive supply voltage for the device. A 0.
Pin descriptions STM6519 3 Pin descriptions 3.1 Power supply (VCC) This pin is used to provide power to the Smart Reset device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the VCC and VSS pins, as close to the STM6519 device as possible. 3.
STM6519 4 Typical application diagrams Typical application diagrams Figure 5. Typical application diagram - input, output and STM6519 device in one voltage domain Figure 6. Typical application diagram - STM6519 device in a different voltage domain than input and output 1. Open-drain RST output type and fixed SR input logic threshold allows to use the device in different voltage domains. To prevent entering test mode by creating a condition V(SR) > VCC + 1.1 V typ.
Typical application diagrams Figure 7.
STM6519 Timing diagrams 5 Timing diagrams Figure 8. RST output without tREC option 1. VCC should be powered up before or together with voltage on the SR input to prevent entering test mode by creating a condition V(SR) > V CC +1.1 V typ. Figure 9. RST output with tREC option 1. VCC should be powered up before or together with voltage on the SR input to prevent entering test mode by creating a condition V(SR) > V CC +1.1 V typ.
Typical operating characteristics 6 STM6519 Typical operating characteristics Figure 10. Supply current (ICC) vs. temperature (TA) 6## 6 6## 6 6## 6 4EMPERATURE 4! # !- Figure 11. Smart Reset delay (tSRC) vs. temperature (TA), tSRC = 4.0 s (typ.
STM6519 Typical operating characteristics Figure 12. Test mode entry voltage (VTEST) vs. temperature (TA) 4EST MODE ENTRY VOLTAGE 64%34 6 6## 6 6## 6 6## 6 4EMPERATURE 4! # !- Figure 13. Initial test mode time (tSRC-INI) vs. temperature (TA) )NITIAL TEST MODE TIME T 32#?).
Maximum ratings 7 STM6519 Maximum ratings Stressing the device above the rating listed in Table 2: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in Table 3: Operating and measurement conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
STM6519 8 DC and AC parameters DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in Table 4: DC and AC characteristics are derived from tests performed under the measurement conditions summarized in Table 3: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 3.
DC and AC parameters Table 4. DC and AC characteristics Symbol Parameter VCC Supply voltage ICC Supply current VOL tREC STM6519 Reset output voltage low Reset timeout delay, factory-programmed Test conditions(1) Min. Typ.(2) Max. Unit 5.5 V 1.0 µA VCC ≥ 4.5 V, sinking 3.2 mA 0.3 V VCC ≥ 3.3 V, sinking 2.5 mA 0.3 V VCC ≥ 2.0 V, sinking 1 mA 0.3 V 2.0 SR = VCC, tREC and tSRC counter is not running 0.4 0.85 1.28 1.
STM6519 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 14. UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package outline 5$&.
Package information Table 5. STM6519 UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package mechanical data Dimensions Symbol (mm) Note(1) (inches) Min. Typ. Max. Min. Typ. Max. A 0.50 0.55 0.60 0.020 0.022 0.024 A1 0.00 0.02 0.05 0.000 0.001 0.002 A3 0.127 0.005 b 0.20 0.25 0.30 0.008 0.010 0.012 D 1.40 1.45 1.50 0.055 0.057 0.059 E 0.95 1.0 1.05 0.037 0.039 0.041 e L N 0.65 0.30 0.026 0.35 0.40 0.012 4 0.014 0.016 4 1.
STM6519 Package information Figure 16. UDFN6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package outline $ . % ! ! , K E B 5$&. , Table 6. UDFN6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package mechanical data Dimensions Symbol (mm) Note(1) (inches) Min. Typ. Max. Min. Typ. Max. A 0.50 0.55 0.60 0.0197 0.0217 0.0236 A1 0.00 0.02 0.05 0.000 0.0008 0.0020 b 0.18 0.25 0.30 0.0071 0.0098 0.0118 D 1.40 1.45 1.50 0.0551 0.0571 0.0591 E 0.95 1.
Package information STM6519 Figure 17. Footprint recommendation for UDFN6 1.00 mm x 1.45 mm x 0.50 mm, 0.
STM6519 10 Tape and reel information Tape and reel information Figure 18. Carrier tape !- 1. 10-sprocket hole pitch cumulative tolerance ±0.20. Figure 19.
Part numbering STM6519 11 Part numbering Table 7. Ordering information scheme Example: STM6519 A H A R UB 6 F Device type STM6519 Reset (VCC monitoring threshold) voltage VRST A = no V CC monitoring feature Smart Reset setup delay (tSRC)(1) C = factory programmable tSRC = 1.5 s (typ.) H = factory programmable tSRC = 4.0 s (typ.) L = factory programmable tSRC = 6.0 s (typ.) P = factory programmable tSRC = 7.5 s (typ.) U = factory programmable tSRC = 10.0 s (typ.
STM6519 12 Package marking information Package marking information Table 8. Package marking tSRC (s) Smart Reset inputs(1) Output type(2) tREC option(3) Package Topmark STM6519AHARUC6F 4.0 AL OD, AL No tREC UDFN4 HA STM6519ALARUC6F 6.0 AL OD, AL No tREC UDFN4 LA STM6519APARUC6F 7.5 AL OD, AL No tREC UDFN4 PA STM6519AUARUC6F 10.0 AL OD, AL No tREC UDFN4 UA STM6519ACARUB6F 1.5 AL OD, AL No tREC UDFN6 CA STM6519AHARUB6F 4.
Revision history 13 STM6519 Revision history Table 9. Document revision history Date Revision 12-Aug-2011 1 Initial release. 22-Sep-2011 2 Updated Figure 5, Table 4, Table 7 and Table 8. 07-Oct-2011 3 Removed label “Preliminary data”. 27-Oct-2011 4 Updated Figure 3 and Table 1. 13-Jun-2012 5 Updated Features, Table 4, title of Section 9. 6 Moved Figure 4 below Table 1. Added Section 3.2, Section 3.6, Figure 6 and Figure 7. Updated title of Figure 5.
STM6519 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.
