Datasheet

STM6513 Block diagram
Doc ID 16490 Rev 2 11/29
STM6513 hookup with RST1 and RST2, bridging the PS_hold reset pulse during the
microprocessor reset initiated by the STM6513 Smart Reset device:
Figure 4. Typical application diagram
Figure 5. Timing waveforms
AM00375a
V
CC
PMU
Seq.
logic
LD00
...
LD07
PWR
SW
POWER
KEY
RST_n
PS_hold
V
REG
STM6513
TSR
TREC
ADJ
RST1 (PP)
RST2 (OD)
SR0
SR1
V
REG
(PU resistor)
MCU
RST
PS_hold
GPIO1 GPIOn
KEYn
KEY1
Forces PS_hold
high during
reset period
C
tREC
100 kΩ
Factory -
programmed
t
REC2
t
REC1
t
REC1
t
SRC
t
REC2
AM00376V2
POR initiated
SR0, SR1
RST2 (OD)
RST1 (PP)
by C
tREC
(210 ms)
(~1 s)
(~1 s)
Smart Reset™ initiated
(210 ms)