STM6513 Reset TM Dual push-button Smart with dual reset outputs and user-selectable setup delay Features ■ Dual Smart Reset push-button inputs with user-selectable extended reset setup delay (by three-state input logic): tSRC = 2, 6, 10 s (min.) ■ Capacitor-adjustable reset pulse duration (tREC1) ■ Power-on reset ■ Dual reset output (RST1 is active-high, pushpull type, RST2 is active-low, open-drain) ■ Factory-programmable thresholds to monitor VCC in the range of 1.575 to 4.625 V typ.
Contents STM6513 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Ground (VSS) . . . . . . . . . .
STM6513 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 tREC1 programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of figures STM6513 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. 4/29 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STM6513 1 Description Description The STM6513 has two separate delayed Smart Reset inputs (SR0, SR1) which when taken low simultaneously provide three user-selectable delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10 s. These are selected through a three-state TSR input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all the times are minimum).
Description STM6513 Figure 1. Logic diagram VCC SR1 TRECADJ STM6513 RST1 RST2 SR0 TSR VSS Figure 2.
STM6513 2 Device overview Device overview Table 1. Signal names Symbol Input/output Description RST1 Output First reset output, active-high, push-pull. RST2 Output Second reset output, active-low, open-drain. SR0 Input Primary push-button Smart Reset input. Active-low. SR1 Input Secondary push-button Smart Reset input. Active-low. TSR Input A Three-state Smart Reset input delay setup control.
Pin descriptions 3 Pin descriptions 3.1 Power supply (VCC) STM6513 This pin is used to provide the power to the Smart Reset device and to monitor the power supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between VCC and VSS pins. 3.2 Ground (VSS) This is the ground for the device and all supplies. 3.3 Smart Reset inputs (SR0, SR1) Push-button Smart Reset inputs. Both inputs need to be held active at the same time for at least tSRC to activate the reset outputs.
STM6513 Pin descriptions Table 2. tREC1 programmed by an ideal external capacitor tREC1 (ms)(1)(2) Closest common CtREC value (µF) Min. Typ. Max. CtREC value (µF) 0.001 10 15 20 0.001 0.002 20 30 40 0.0022 0.01 100 150 200 0.01 0.014 140 210 280 0.015 0.028 280 420 560 0.027 0.056 560 840 1120 0.056 0.112 1120 1680 2240 0.12 1. At 25 ° C. Example calculations based on an ideal capacitor.
Block diagram STM6513 4 Block diagram Figure 3.
STM6513 Block diagram STM6513 hookup with RST1 and RST2, bridging the PS_hold reset pulse during the microprocessor reset initiated by the STM6513 Smart Reset device: Figure 4. Typical application diagram VCC PMU VREG LD00 ... LD07 MCU Seq. logic (PU resistor) RST_n RST PWR SW POWER KEY PS_hold PS_hold 100 kΩ VREG GPIO1 RST1 (PP) RST2 (OD) TSR TRECADJ STM6513 SR0 GPIOn Forces PS_hold high during reset period SR1 KEYn CtREC KEY1 AM00375a Figure 5.
Typical operating characteristics 5 STM6513 Typical operating characteristics Figure 6. Smart Reset delay tSRC vs. temperature and supply voltage VCC, TSR = VSS 3 2.9 2.8 2.7 2.6 2.5 tSRC [s] 2.4 2.3 2.2 2.1 2 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] 5.5 V 3.
STM6513 Typical operating characteristics Figure 7. Output reset timeout period tREC2 vs. temperature and supply voltage VCC (tREC option E) 280 260 240 220 tREC2 [ms] 200 180 160 140 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] 5.5 V 3.3 V AM00633 Supply current ICC vs. temperature and supply voltage VCC Figure 8. 6 5 4 3 ICC [µA] 2 1 0 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] 5.5 V 3.
Typical operating characteristics Figure 9. STM6513 Reset voltage VRST (falling) vs. temperature (threshold option S, 2.925 V typ.) 2.96 2.95 2.94 2.93 VRST, falling [V] 2.92 2.91 2.9 2.89 –60 –40 –20 0 20 40 60 80 100 120 140 Temperature [˚C] AM00635 Figure 10. Input leakage current, TSR pin, logic low vs. temperature and supply voltage VCC 10 8 6 4 2 ILI(TSR) , LO [µA] –60 –40 –20 0 0 20 40 60 80 100 120 140 –2 –4 –6 –8 –10 Temperature [˚C] 5.5 V 3.
STM6513 Typical operating characteristics Figure 11. Input leakage current, TSR pin, logic high vs. temperature and supply voltage VCC 10 8 6 4 2 ILI(TSR), HI [µA] 0 –60 –40 –20 0 20 40 60 80 100 120 140 –2 –4 –6 –8 –10 Temperature [˚C] 5.5 V 3.
Maximum rating 6 STM6513 Maximum rating Stressing the device above the rating listed in the Table 3: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
STM6513 7 DC and AC parameters DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the Table 5: DC and AC characteristics that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4.: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4.
DC and AC parameters Table 5. STM6513 DC and AC characteristics Symbol Parameter VCC Supply voltage range Test conditions(1) Min. 5.5 V Reset output valid - active-high 1.2 5.5 V 3 5 µA 4 6 µA 0.3 V 0.3 V 0.3 V VCC = 3.0 V, TSR left open (3) VOL VCC ≥ 4.5 V, sinking 3.2 mA Reset output voltage VCC ≥ 3.3 V, sinking 2.5 mA low VCC ≥ 1.0 V, sinking 0.1 mA VCC = 5.0 V, TSR left open VCC ≥ 4.5 V, ISOURCE = 0.8 mA Reset output voltage VCC ≥ 2.7 V, ISOURCE = 0.
STM6513 DC and AC parameters Table 5. DC and AC characteristics (continued) Symbol Test conditions(1) Min. Typ.(2) Max. Units TSR = VSS 2 2.5 3 s TSR = floating 6 7.5 9 s TSR = VCC 10 12.5 15 s Parameter Smart Reset inputs (SRx) tSRC Smart Reset delay VIL SR0, SR1 input voltage low VSS –0.3 0.3 VCC V VIH SR0, SR1 input voltage high 0.7 VCC 5.
Package mechanical data 8 STM6513 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. TDFN - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch D A B PIN 1 INDEX AREA E 0.10 C 2x 0.10 C 2x TOP VIEW 0.10 C C A1 A SEATING PLANE SIDE VIEW 0.
STM6513 Package mechanical data Table 7. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data Dimension (mm) Dimension (inches) Symbol Min. Nom. Max. Min. Nom. Max. A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D BSC 1.9 2.00 2.1 0.075 0.079 0.083 E BSC 1.9 2.00 2.1 0.075 0.079 0.083 e L 0.50 0.45 0.55 0.020 0.65 Doc ID 16490 Rev 2 0.018 0.022 0.
Package footprint 9 STM6513 Package footprint Figure 14. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad D P E E1 L b Table 8. AM00441 Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package Dimension (mm) Parameter 22/29 Description Min. Nom. Max. L Contact length 1.05 — 1.15 b Contact width 0.25 — 0.30 E Max. land pattern Y-direction — 2.85 — E1 Contact gap spacing — 0.65 — D Max. land pattern X-direction — 1.75 — P Contact pitch — 0.
STM6513 10 Tape and reel information Tape and reel information Figure 15. Carrier tape P0 D P2 T E A0 F Top cover tape W B0 Center lines of cavity K0 P1 User direction of feed AM03073v2 Table 9. Carrier tape dimensions Package W D TDFN8 8.00 +0.30 –0.10 1.50 +0.10/ –0.00 E P0 P2 F 1.75 4.00 2.00 3.50 ±0.10 ±0.10 ±0.10 ±0.05 A0 B0 K0 P1 T 2.30 ±0.05 2.30 ±0.05 1.00 ±0.05 4.00 ±0.10 0.250 ±0.05 Doc ID 16490 Rev 2 Unit Bulk qty.
Tape and reel information STM6513 Figure 16. Reel dimensions T 40 mm min. acces hole at slot location B D C N A Full radius Tape slot in core for tape start 25 mm min width G measured at hub AM00443 Table 10. 24/29 Reel dimensions Tape sizes A max. B min. C D min. N min. G T max. 8 mm 180 (7 inches) 1.50 13.0 +/– 0.20 20.20 60 8.4 +2/–0 14.
STM6513 Tape and reel information Figure 17. Tape trailer/leader End Top cover tape Start No components Components 100 mm min. T RA IL ER No components L EA D ER 160 mm min. 400 mm min. Sealed with cover tape User direction of feed AM00444 Figure 18. Pin 1 orientation User direction of feed Note: 1 Drawings are not to scale. 2 All dimensions are in mm, unless otherwise noted.
Part numbering STM6513 11 Part numbering Table 11. Ordering information scheme Example: STM6513 V E I E DG 6 Device type STM6513 Reset (VCC monitoring threshold) voltage VRST L = 4.625 V (typ., falling) M = 4.375 V T = 3.075 V S = 2.925 V R = 2.625 V Z = 2.313 V Y = 2.188 V W = 1.665 V V = 1.575 V Smart Reset setup delay (tSRC); presence of internal input pull-up on all Smart Reset inputs (SR0, SR1) E = 2 or 6 or 10 s min.
STM6513 Package marking information 12 Package marking information Table 12.
Revision history 13 STM6513 Revision history Table 13. Document revision history Date Revision 22-Oct-2009 1 Initial release. 2 Updated title, Features, Applications, replaced “smart reset” by “Smart Reset™” and “Smart Reset”, updated Section 1, Table 1, Section 3, Table 2, Figure 3, Figure 5, Figure 6, Table 3, Table 5 to Table 8, Table 11 and Table 12.
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