Datasheet

Description STM6502, STM6503, STM6504, STM6505
8/29 Doc ID 16101 Rev 6
Figure 3. Block diagram - STM6502, STM6503, STM6504
1. STM6504 only: SR0 and SRE are working independently. SRE is edge-triggered and has a special
debounce time (t
DEBOUNCE
= 240 ms min.) at the falling edge after a valid reset period.
Figure 4. Block diagram - STM6505
V
CC
V
RST
COMPARE
SR0
SRC (STM6502)
TSR (STM6503,
STM6504)
RST
t
REC
generator
Logic
SR1
(SRE
STM6504
only)
(1)
Logic
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