Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsPMICsPMIC - system monitor Reset timer TDFN 8

February 2011 Doc ID 16101 Rev 6 1/29

STM6502, STM6503

STM6504, STM6505

Dual push-button Smart Reset

with user-adjustable setup delays

Features

■ Dual Smart Reset push-button inputs with

extended reset setup delay

■ Adjustable Smart Reset setup delay (t

SRC

by external capacitor or three-state logic

(product options): t

SRC

= 2, 6, 10 s (min.)

■ Power-on reset

■ Single RST output, active-low, open-drain

■ Factory-programmable thresholds to monitor

in the range of 1.575 to 4.625 V typ.

■ Operating voltage 1.0 V (active-low output

valid) to 5.5 V

■ Low supply current

■ Operating temperature:

industrial grade –40 °C to +85 °C

■ TDFN8 package: 2 mm x 2 mm x 0.75 mm

■ RoHS compliant

Applications

■ Mobile phones, smartphones

■ e-books

■ MP3 players

■ Games

■ Portable navigation devices

■ Any application that requires delayed reset

push-button(s) response for improved system

stability

TDFN8 (DG)

2 mm x 2 mm

Table 1. Device summary

Part

number

Voltage inputs Smart Reset inputs

SRC

programming

Reset or Power

Good outputs

Package

BAT

SR0 SR1

SRE

immediate,

independent

Ext.

SRC pin

Three-

state

input

TSR

RST

BLD

STM6502

(1)

✓✓✓ ✓ ✓TDFN-8L

STM6503 ✓✓✓ ✓✓TDFN-8L

STM6504

(1)

✓✓ ✓ ✓✓TDFN-8L

STM6505 ✓✓ ✓ ✓ ✓ ✓ ✓TDFN-8L

1. Contact local ST sales office for availability.

www.st.com

Summary of content (29 pages)

PAGE 1
STM6502, STM6503 STM6504, STM6505 Dual push-button Smart ResetTM with user-adjustable setup delays Features ■ Dual Smart Reset push-button inputs with extended reset setup delay ■ Adjustable Smart Reset setup delay (tSRC): by external capacitor or three-state logic (product options): tSRC = 2, 6, 10 s (min.) ■ Power-on reset ■ Single RST output, active-low, open-drain ■ Factory-programmable thresholds to monitor VCC in the range of 1.575 to 4.625 V typ. ■ Operating voltage 1.
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Contents STM6502, STM6503, STM6504, STM6505 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Smart Reset devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.
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STM6502, STM6503, STM6504, STM6505 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM6502, STM6503, STM6504, STM6505 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Logic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM6502, STM6503, STM6504, STM6505 1 Description Description STM6502 has two combined Smart Reset inputs (SR0 and SR1) with delayed Smart Reset setup time (tSRC) programmed by an external capacitor on the SRC pin.
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Description STM6502, STM6503, STM6504, STM6505 The STM65xx devices have active-low (optionally active-high) open-drain reset (RST) output(s) with or without internal pull-up resistor or push-pull as output options, with factoryprogrammed or capacitor-adjustable or push-buttons defined output reset pulse duration, with or without power-on reset function.
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STM6502, STM6503, STM6504, STM6505 Table 2. Description Signal names Symbol Input/ output RST Output Open-drain reset output, active-low. BLD Output Battery low detect output, active-low, open-drain. STM6505 only. SR0 Input Primary push-button Smart Reset input. Active-low, with or without internal 65 kΩ pull-up to VCC (product options). SR1 Input Secondary push-button Smart Reset input - combines with the primary pushbutton reset to provide setup delay time before reset.
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Description STM6502, STM6503, STM6504, STM6505 Figure 3. Block diagram - STM6502, STM6503, STM6504 VCC SR1 (SRE STM6504 only)(1) SR0 SRC (STM6502) TSR (STM6503, STM6504) VRST COMPARE Logic tREC generator RST Logic AM00352a 1. STM6504 only: SR0 and SRE are working independently. SRE is edge-triggered and has a special debounce time (tDEBOUNCE = 240 ms min.) at the falling edge after a valid reset period. Figure 4.
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STM6502, STM6503, STM6504, STM6505 Figure 5. Description Single-button Smart Reset typical hookup 6## 6## 2%3%4 234 6## 432 34- -#5 32 ).4 .-) 32 633 633 053( "544/. 37)4#( !- B Figure 6. Dual-button Smart Reset typical hookup 6## 6## 234 2%3%4 6## 432 34- -#5 32 ).4 .-) 32 633 053( "544/. 37)4#( 633 053( "544/.
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Description STM6502, STM6503, STM6504, STM6505 1.2 Pin descriptions 1.2.1 Power supply (VCC) This pin is used to provide the power to the device and to monitor the power supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between the VCC and VSS pins. 1.2.2 Ground (VSS) This is the supply ground for the device. 1.2.3 Primary Smart Reset input (SR0) The primary push-button Smart Reset input, active-low pin is connected to the first pushbutton switch. 1.2.
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STM6502, STM6503, STM6504, STM6505 1.2.5 Description Edge-triggered Smart Reset input (SRE pin) – STM6504 only The SRE pin is active-high, immediate and independent reset input that includes an edge trigger with debounce delay tDEBOUNCE on the falling edge. Note: The triggering edge must be a high-to-low or low-to-high transition with a slew-rate faster than 1 V/µs typ. Figure 8.
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Description 1.2.7 STM6502, STM6503, STM6504, STM6505 Programmable Smart Reset input delay (TSR pin) – STM6503 and STM6504 only The TSR pin allows the user to program the setup time before the push-button action is validated by the reset output. It is controlled by different voltage levels on the three-state TSR input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all times are minimum).
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STM6502, STM6503, STM6504, STM6505 2 Typical operating characteristics Typical operating characteristics Figure 10. Supply current (ICC) vs. temperature (STM6505) 3 2.5 ICC [μA] 2 1.5 1 0.5 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] 5.5 V 2V 5V 3V AM04886v1 Figure 11. Smart Reset delay (tSRC) vs. temperature, CSRC = 0.62 µF (STM6505) 9.2 8.7 tSRC [s] 8.2 7.7 7.2 6.7 6.2 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] 5.75 V 5.5 V 3.
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Typical operating characteristics STM6502, STM6503, STM6504, STM6505 Figure 12. Reset threshold (VRST) vs. temperature, “S” threshold option, VCC falling (STM6505) 2.99 2.97 VRST [V] 2.95 2.93 2.91 2.89 2.87 2.85 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] AM04888v1 Figure 13. VBAT monitoring threshold (VBATTH) vs. temperature, falling (STM6505) 1.275 1.27 1.265 1.26 VBATTH [V] 1.255 1.25 1.245 1.24 1.235 1.23 1.
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STM6502, STM6503, STM6504, STM6505 3 Maximum ratings Maximum ratings Stressing the device above the rating listed in Table 4: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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DC and AC parameters 4 STM6502, STM6503, STM6504, STM6505 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 5: Operating and measurement conditions.
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STM6502, STM6503, STM6504, STM6505 Table 6. DC and AC characteristics Symbol VCC DC and AC parameters Test conditions(1) Parameter Supply voltage range Reset output valid - active-low STM6502 ICC STM6503 (3) VCC = 5.0 V, TSR left open VCC = 3.0 V, TSR left open STM6504 STM6505 Unit 5.5 V µA 1.1 µA 5.8 3 4 (3) 2.3 V(3) µA µA 5.8 3 VCC = 5.0 V VCC = 3.0 Max. 1.2 4 (3) VCC = 5.0 V, TSR left open VCC = 3.0 V, TSR left open Typ.(2) 1.0 VCC = 5.0 V VCC = 3.
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DC and AC parameters Table 6. STM6502, STM6503, STM6504, STM6505 DC and AC characteristics (continued) Symbol Test conditions(1) Parameter Min. Typ.(2) Max. Unit Smart Reset inputs VIL SR0, SR1, SRE input voltage low VSS –0.3 0.3 VCC V VIH SR0, SR1, SRE input voltage high 0.7 VCC 5.
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STM6502, STM6503, STM6504, STM6505 . Table 7. DC and AC parameters VCC voltage thresholds VCC monitoring threshold VRST ±2.5% (–40 °C to +85 °C) ±2.0% (25 °C) Typ. Unit Min. Max. Min. Max. L (falling) 4.625 4.509 4.741 4.533 4.718 V M (falling) 4.375 4.266 4.484 4.288 4.463 V T (falling) 3.075 2.998 3.152 3.014 3.137 V S (falling) 2.925 2.852 2.998 2.867 2.984 V R (falling) 2.625 2.559 2.691 2.573 2.678 V Z (falling) 2.313 2.255 2.371 2.267 2.
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Package mechanical data 5 STM6502, STM6503, STM6504, STM6505 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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STM6502, STM6503, STM6504, STM6505 Package mechanical data Figure 15. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline D A B PIN 1 INDEX AREA E 0.10 C 2x 0.10 C 2x TOP VIEW 0.10 C C A1 A SEAT ING PLANE SIDE VIEW 0.08 C e b PIN 1 INDEX AREA 1 4 0.10 C A B Pin#1 ID L 5 8 BOTTOM VIEW 8070540_A Table 8. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data Dimension (mm) Dimension (inches) Symbol Min. Nom. Max. Min. Nom. Max. A 0.70 0.75 0.80 0.028 0.
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Package mechanical data STM6502, STM6503, STM6504, STM6505 Figure 16. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad D P E E1 L b Table 9. AM00441 Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package Dimension (mm) Parameter 22/29 Description Min. Nom. Max. L Contact length 1.05 — 1.15 b Contact width 0.25 — 0.30 E Max. land pattern Y-direction — 2.85 — E1 Contact gap spacing — 0.65 — D Max. land pattern X-direction — 1.
PAGE 23
STM6502, STM6503, STM6504, STM6505 Package mechanical data Figure 17. Carrier tape P0 D P2 T E A0 F Top cover tape W B0 Center lines of cavity K0 P1 User direction of feed AM03073v2 Table 10. Carrier tape dimensions Package W D TDFN8 8.00 +0.30 –0.10 1.50 +0.10/ –0.00 E P0 P2 F 1.75 4.00 2.00 3.50 ±0.10 ±0.10 ±0.10 ±0.05 A0 B0 K0 P1 T 2.30 ±0.05 2.30 ±0.05 1.00 ±0.05 4.00 ±0.10 0.250 ±0.05 Doc ID 16101 Rev 6 Unit Bulk qty.
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Package mechanical data STM6502, STM6503, STM6504, STM6505 Figure 18. Reel dimensions T 40 mm min. acces hole at slot location B D C N A Full radius Tape slot in core for tape start 25 mm min width G measured at hub AM00443 Table 11. Reel dimensions Tape sizes A max. B min. C D min. N min. G T max. 8 mm 180 (7 inches) 1.50 13.0 +/– 0.20 20.20 60 8.4 +2/–0 14.
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STM6502, STM6503, STM6504, STM6505 Package mechanical data Figure 19. Tape trailer/leader End Top cover tape Start No components Components 100 mm min. T RA IL ER No components L EA D ER 160 mm min. 400 mm min. Sealed with cover tape User direction of feed AM00444 Figure 20. Pin 1 orientation User direction of feed AM00442 Note: 1 Drawings are not to scale. 2 All dimensions are in mm, unless otherwise noted.
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Part numbering STM6502, STM6503, STM6504, STM6505 6 Part numbering Table 12. Ordering information scheme Example: STM6505 W C A B DG 6 F Device type STM6502(1) STM6503 STM6504(1) STM6505 Reset (VCC monitoring) threshold voltage (VRST), typ., falling L = 4.625 V S = 2.925 V R = 2.625 V Z = 2.313 V W = 1.665 V V = 1.
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STM6502, STM6503, STM6504, STM6505 7 Package marking Package marking Table 13.
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Revision history 8 STM6502, STM6503, STM6504, STM6505 Revision history Table 14. 28/29 Document revision history Date Revision Changes 31-Aug-2009 1 Initial release. 06-Nov-2009 2 Updated Applications, Section 1, Section , Figure 3 to Figure 6 updated and moved to Section , updated Table 1, Table 2, Table 3, Table 4, Table 6, Table 12, Section 1.2.3, Section 1.2.7, Section 1.2.9, Section 5, added package footprint, tape and reel information, and Section 7.
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STM6502, STM6503, STM6504, STM6505 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.