Datasheet

DocID022799 Rev 6 21/132
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC Functional overview
51
Figure 2. Clock tree
1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
24 MHz or 32 MHz.
MS18583V1
LSI RC
LSE OSC
HSI RC
HSE
OSC
@V33
@V
DDCORE
@V33
level shifters
level shifters
RTC
PLL
X 3,4,6,8,12
@V33
level shifters
LSE tempo
1 MHz clock
detector
@V33
LS
Watchdog
ck_pllin
source
control
Clock
Watchdog
enable
RTC enable
ck_hsi
ck_hse
HSE present or not
LSI tempo
ck_pll
AHB
prescaler
/ 1,2,..512
APB2
/ 1,2,4,8,16
APB1
/ 1,2,4,8,16
ck_usb = Vco / 2 (Vco must be at 96 MHz)
/ 8
CK_TIMSYS
CK_CPU
CK_FCLK
CK_PWR
CK_USB48
CK_TIMTGO
CK_APB1
CK_APB2
usben and (not deepsleep)
timer9en and (not deepsleep)
apb1 periphen and (not deepsleep)
apb2 periphen and (not deepsleep)
not (sleep or
deepsleep)
not (sleep or
deepsleep
not deepsleep
not deepsleep
Standby supplied voltage domain
System
clock
MCO
if (APB1 presc = 1)
x1
else
x2
16,24,32,48
ck_lse
CK_LCD
/ 2, 3, 4
1 MHz
@V
DDCORE
@V
DDCORE
@V
DDCORE
/ 1,2,4,8,16
LCD enable
MSI RC
@V33
@V
DDCORE
level shifters
ck_msi
ck_lsi
CK_ADC
ADC enable
LS LS LS LS
LS
LS
/ 2,4,8,16
prescaler prescaler