Datasheet

Functional overview STM32L151x6/8/B, STM32L152x6/8/B
28/131 DocID17659 Rev 9
3.15.5 Window watchdog (WWDG)
The window watchdog is based on a 7-bit down-counter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.16 Communication interfaces
3.16.1 I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
3.16.2 Universal synchronous/asynchronous receiver transmitter (USART)
All USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They provide
hardware management of the CTS and RTS signals. They support IrDA SIR ENDEC, are
ISO 7816 compliant and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
3.16.3 Serial peripheral interface (SPI)
Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
3.16.4 Universal serial bus (USB)
The STM32L15xxx embeds a USB device peripheral compatible with the USB full speed
12 Mbit/s. The USB interface implements a full speed (12 Mbit/s) function interface. It has
software-configurable endpoint setting and supports suspend/resume. The dedicated
48 MHz clock is generated from the internal main PLL (the clock source must use a HSE
crystal oscillator).