Datasheet

Functional overview STM32L151x6/8/B, STM32L152x6/8/B
12/131 DocID17659 Rev 9
3 Functional overview
Figure 1 shows the block diagrams.
Figure 1. Ultralow power STM32L15xxx block diagram
1. AF = alternate function on I/O port pin.
EXT. IT
WWDG
12-bit ADC
JTAG &SW
24 A F
JT D I
JT CK/ S WCLK
JTMS /SWDAT
NJT R ST
JTDO
NRST
V
DD
=1. 65 V to 3.6 V
83A F
AH B2
US B_DP
US B_DM
MO S I,MIS O, S CK, NS S
WKU P
F
ma x
:32MHz
V
SS
S C L, SD A, SMB u s ,P MB us
I2C 2
V
DDREF _ADC
*
GP DMA
TIM2
TIM3
X T AL O S C
1-24 MHz
X T A L 32 kHz
OSC_IN
OSC_OUT
OS C32 _OUT
OS C32 _IN
PLL &
APB1 : F
ma x
=32MHz
A HBP CL K
HC L K
clock
management
AP BP CL K
as AF
as AF
VOLT. RE G.
V
CO R E
PO W E R
as A F
TIM4
B us Matrix
Interface
RT C
RC HS
Ibus
Db us
pbus
obl
Flash
US B RAM 512 B
US ART 1
US ART 2
SP I2
7 c hannels
SC L, S D A
I2C 1
as AF
RX ,T X , CT S , RT S ,
US ART 3
Te mp s ens or
V
SS REF_ ADC
*
AHB:F
max
=32 MHz
4Channels
4Channels
4Channels
FC LK
IWDG
@V DD
Supply
monitoring
@V DD A
VDDA /
VSS A
@V DD A
S martC ard a s AF
RX ,T X , C T S, R T S,
S mar tC ard as AF
RX ,TX, C T S, R T S,
S m artCa rd as A F
AP B2 : F
ma x
=32 MHz
NV IC
SPI 1
MOSI ,MIS O,
SC K, NS S as AF
IF
@VD D A
PV D
Power reset
Int
AHB 2
AW U
@V DD A
RTC_OUT, RTC_TS,RTC_TAMP
System
P A [15:0 ]
P B [15:0 ]
P C [15:0 ]
PD[ 15:0]
PE[1 5:0 ]
LCD 8x4 0 (4x44 )
SEG x
COM x
IFIFIF
@V DD A
DAC_OUT1 as AF
MP U
Co mp 2
COMP2 _IN- /IN +
Co mp 1
TIM6
TIM7M
TI M9
TI M10
TI M11
2 Channe ls
1 C hannel
1 Channel
General purpose
timers
128 KB Flash
4 KB data EEPROM
LCD step-up
converter
V
LCD
=2.5 V to 3.6 V
V
LC D
BA SI C T IME RS
RTC_AFIN
VR EF O UTPU T
Ai15687h
Cortex-M3 CPU
Trace controller
ETM
RAM
16 KB
12-bit DAC1
12-bit DAC2
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
TRACECK, TRACED0, TRACED1, TRACED2, TRACED3
RC MS
RC LS
Standby interface
Backup interface
USB 2.0 FS device
BOR/V
REFINT
Power-up/
Power-down
Backup
register
PH[2 :0 ]
GPIOH
DAC_OUT2 as AF
AHB/APB2 AHB/APB1