Datasheet

Revision history STM32L151x6/8/B, STM32L152x6/8/B
126/131 DocID17659 Rev 9
25-Feb-2011
4
(continued)
Updated Table 23: Typical and maximum current consumptions in
Standby mode on page 65 (I
DD
(WU from Standby) instead of (I
DD
(WU from Stop).
Table 25: Low-power mode wakeup timings on page 68: updated
condition for Wakeup from Stop mode, regulator in Run mode;
updated max values for Wakeup from Stop mode, regulator in low
power mode; updated max values for t
WUSTDBY
.
Table 24: Peripheral current consumption on page 66: updated
values for column Low power sleep and run; updated Flash values;
renamed ADC1 to ADC; updated I
DD (LCD)
value; updated units;
added values for I
DD (RTC)
and I
DD (IWDG)
; updated footnote 1 and 3;
added foot note 2 concerning ADC.
Table 26: High-speed external user clock characteristics on
page 69: added min value for t
w(HSE)
/t
w(HSE)
OSC_IN high or low
time; added max value for t
r(HSE)
/t
f(HSE)
OSC_IN rise or fall time;
updated I
L
for typ and max values.
Table 27: Low-speed external user clock characteristics on page 70:
updated max value for I
L
.
Table 28: HSE oscillator characteristics on page 71: renamed i
2
as
I
HSE
and updated max value; updated max values for I
DD(HSE)
.
Table 29: LSE oscillator characteristics (fLSE = 32.768 kHz) on
page 72: updated max value for I
LSE
.
Table 30: HSI oscillator characteristics on page 74: updated some
min and max values for ACC
HSI
.
Table 32: MSI oscillator characteristics on page 75: updated
parameter, typ, and max values for D
VOLT(MSI)
.
Table 35: Flash memory and data EEPROM characteristics on
page 77: updated typ values for t
prog
.
Table 44: I/O AC characteristics on page 84: updated some max
values for 01, 10, and 11; updated min value; updated footnotes.
Table 55: ADC accuracy on page 96: updated typ values and some
of the test conditions for ENOB, SINAD, SNR, and THD.
Table 57: DAC characteristics on page 100: updated footnote 7 and
added footnote 8.
Updated leakage value in Figure 27: Typical connection diagram
using the ADC.
Added Figure 28: Maximum dynamic current consumption on
VREF+ supply pin during ADC conversion.
Added Table 56: RAIN max for fADC = 16 MHz on page 98
Figure 29: Power supply and reference decoupling (VREF+ not
connected to VDDA): replaced all 10 nF capacitors with 100 nF
capacitors.
Figure 30: Power supply and reference decoupling (VREF+
connected to VDDA): replaced 10 nF capacitor with 100 nF
capacitor.
Table 71. Document revision history (continued)
Date Revision Changes