Datasheet

STM32L100C6, STM32L100R8/RB Electrical characteristics
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6.3.15 Communication interfaces
I
2
C interface characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under ambient temperature, fPCLK1 frequency and VDD supply voltage
conditions summarized in Table 12.
The STM32L100C6 product line
I
2
C interface meets the requirements of the standard I
2
C
communication protocol with the following restrictions: SDA and SCL are not “true” open-
drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin
and V
DD
is disabled, but is still present.
The I
2
C characteristics are described in Table 45. Refer also to Section 6.3.11: I/O current
injection characteristics
for more details on the input/output alternate function characteristics
(SDA and SCL)
.
Table 45. I
2
C characteristics
Symbol Parameter
Standard mode I
2
C
(1)
1.
Guaranteed by design, not tested in production.
Fast mode I
2
C
(1)(2)
2. f
PCLK1
must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
Unit
Min Max Min Max
t
w(SCLL)
SCL clock low time 4.7 1.3
µs
t
w(SCLH)
SCL clock high time 4.0 0.6
t
su(SDA)
SDA setup time 250 100
ns
t
h(SDA)
SDA data hold time 0 0 900
(3)
3.
The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
t
r(SDA)
t
r(SCL)
SDA and SCL rise time 1000 20 + 0.1C
b
300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time 300 300
t
h(STA)
Start condition hold time 4.0 0.6
µs
t
su(STA)
Repeated Start condition
setup time
4.7 0.6
t
su(STO)
Stop condition setup time 4.0 0.6 μs
t
w(STO:STA)
Stop to Start condition time
(bus free)
4.7 1.3 μs
C
b
Capacitive load for each bus
line
400 400 pF