Datasheet

Electrical characteristics STM32L100C6, STM32L100R8/RB
76/102 DocID024295 Rev 1
Figure 15. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 43. Otherwise the reset will not be taken into account by the device.
6.3.14 TIM timer characteristics
The parameters given in the following table are guaranteed by design.
Refer to Section 6.3.11: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).
AI
34-,XX
2
05
.234

6
$$
&ILTER
)NTERNALRESET
&
%XTERNAL
RESETCIRCUIT

Table 44. TIMx
(1)
characteristics
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
Symbol Parameter Conditions Min Max Unit
t
res(TIM)
Timer resolution time
1
t
TIMxCLK
f
TIMxCLK
= 32 MHz 31.25 ns
f
EXT
Timer external clock
frequency on CH1 to CH4
0
f
TIMxCLK
/2
MHz
f
TIMxCLK
= 32 MHz 0 16 MHz
Res
TIM
Timer resolution 16 bit
t
COUNTER
16-bit counter clock period
when internal clock is
selected (timer’s prescaler
disabled)
1 65536
t
TIMxCLK
f
TIMxCLK
= 32 MHz 0.0312 2048 µs
t
MAX_COUNT
Maximum possible count
65536 × 65536
t
TIMxCLK
f
TIMxCLK
= 32 MHz 134.2 s