Datasheet

Electrical characteristics STM32L100C6, STM32L100R8/RB
72/102 DocID024295 Rev 1
6.3.12 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under conditions summarized in Table 12. All I/Os are CMOS and TTL compliant.
Table 40. I/O static characteristics
Symbol Parameter Conditions Min Typ
Max Unit
V
IL
Input low level voltage
TTL ports
2.7 V V
DD
3.6 V
V
SS
- 0.3 0.8
V
V
IH
Standard I/O input high level voltage
2
(1)
V
DD
+0.3
FT
(2)
I/O input high level voltage 5.5V
V
IL
Input low level voltage
CMOS ports
1.8 V
V
DD
3.6 V
–0.3 0.3V
DD
(3)
V
IH
Standard I/O Input high level voltage
CMOS ports
1.8 V
V
DD
3.6 V
0.7
V
DD
(3)(4)
V
DD
+0.3
FT
(5)
I/O input high level voltage
CMOS ports
1.8 V
V
DD
2.0 V
5.25
CMOS ports
2.0 V
V
DD
3.6 V
5.5
V
hys
Standard I/O Schmitt trigger voltage
hysteresis
(6)
10% V
DD
(7)
I
lkg
Input leakage current
(8)(3)
V
SS
V
IN
V
DD
I/Os with LCD
±50
nA
V
SS
V
IN
V
DD
I/Os with analog switches
±50
V
SS
V
IN
V
DD
I/Os with analog switches
and LCD
±50
V
SS
V
IN
V
DD
I/Os with USB
TBD
V
SS
V
IN
V
DD
Standard I/Os
±50
R
PU
Weak pull-up equivalent resistor
(9)(3)
V
IN
= V
SS
30 45 60 kΩ
R
PD
Weak pull-down equivalent
resistor
(9)(3)
V
IN
= V
DD
30 45 60 kΩ
C
IO
I/O pin capacitance 5 pF
1. Guaranteed by design.
2. FT = 5V tolerant. To sustain a voltage higher than V
DD +0.5 the internal pull-up/pull-down resistors must be disabled.
3. Tested in production
4. 0.7V
DD
for 5V-tolerant receiver
5. FT = Five-volt tolerant.
6. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
7. With a minimum of 200 mV. Based on characterization, not tested in production.
8. The max. value may be exceeded if negative current is injected on adjacent pins.
9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum
(~10% order).