Datasheet

STM32L100C6, STM32L100R8/RB Electrical characteristics
DocID024295 Rev 1 57/102
APB2
SYSCFG &
RI
32.522.5
µA/MHz
(f
HCLK
)
TIM9 9 7.5 6 7
TIM10 6.5 5.5 4.5 5.5
TIM11 7 6 4.5 5.5
ADC
(2)
11.5 9.5 8 9
SPI1 5 4.5 3 4
USART197.567.5
AHB
GPIOA 5 4.5 3.5 4
GPIOB 5 4.5 3.5 4.5
GPIOC 5 4.5 3.5 4.5
GPIOD 5 4.5 3.5 4.5
GPIOE 5 4.5 3.5 4.5
GPIOH 4 4 3 3.5
CRC 1 0.5 0.5 0.5
FLASH 13 11.5 9 18.5
DMA1 12 10 8 10.5
All enabled 166 138 106 130
I
DD (RTC)
0.47
µA
I
DD (LCD)
3.1
I
DD (ADC)
(3)
1450
I
DD (DAC)
(4)
340
I
DD (COMP1)
0.16
I
DD (COMP2)
Slow mode 2
Fast mode 5
I
DD (PVD / BOR)
(5)
2.6
I
DD (IWDG)
0.25
1. Data based on differential I
DD
measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: f
HCLK
= 32 MHz (range 1), f
HCLK
= 16 MHz (range 2), f
HCLK
= 4 MHz
(range 3), f
HCLK
= 64kHz (Low power run/sleep), f
APB1
= f
HCLK
, f
APB2
= f
HCLK
, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. Data based on a differential I
DD measurement between ADC in reset configuration and continuous ADC
conversion (HSI consumption not included).
Table 23. Peripheral current consumption
(1)
(continued)
Peripheral
Typical consumption, V
DD
= 3.0 V, T
A
= 25 °C
Unit
Range 1,
V
CORE
=
1.8 V
VOS[1:0] =
01
Range 2,
V
CORE
=
1.5 V
VOS[1:0] =
10
Range 3,
V
CORE
=
1.2 V
VOS[1:0] =
11
Low power
sleep and
run