Datasheet

Functional overview STM32L100C6, STM32L100R8/RB
24/102 DocID024295 Rev 1
3.10 ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L100xx devices with up to 20
external channels, performing conversions in single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start trigger and injection trigger, to allow the application to synchronize A/D
conversions and timers. An injection mode allows high priority conversions to be done by
interrupting a scan mode which runs in as a background task.
The ADC includes a specific low power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
3.10.1 Internal voltage reference (V
REFINT
)
The internal voltage reference (V
REFINT
) provides a stable (bandgap) voltage output for the
ADC and Comparators. V
REFINT
is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the V
DD
value. The precise voltage of V
REFINT
is
individually measured for each part by ST during production test and stored in the system
memory area. It is accessible in read-only mode.
3.11 DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
• two DAC converters: one for each output channel
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• dual DAC channels’ independent or simultaneous conversions
• DMA capability for each channel (including the underrun interrupt)
• external triggers for conversion
Table 5. Internal voltage reference measured values
Calibration value name Description Memory address
VREFINT_CAL
Raw data acquired at
temperature of 30 °C
V
DDA
= 3 V
0x1FF8 0078-0x1FF8 0079