Datasheet

Functional overview STM32L100C6, STM32L100R8/RB
18/102 DocID024295 Rev 1
Nested vectored interrupt controller (NVIC)
The ultralow power STM32L100xx embeds a nested vectored interrupt controller able to
handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support for tail-chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3 Reset and supply management
3.3.1 Power supply schemes
• V
DD
= 1.8 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through V
DD
pins.
• V
SSA
, V
DDA
= 1.8 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL.
V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
3.3.2 Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
BOR is activated at power-on and the device operate between 1.8 V and 3.6 V.
After the V
DD
threshold is reached, the option byte loading process starts, either to confirm
or modify default thresholds, or to disable the BOR permanently: in this case, the V
DD
min
value becomes 1.65 V.
BOR ensures proper operation starting from 1.8 V whatever the power ramp-up phase
before it reaches 1.8 V.