Datasheet

Functional overview STM32L100C6, STM32L100R8/RB
12/102 DocID024295 Rev 1
3 Functional overview
Figure 1 shows the block diagrams.
Figure 1. Ultralow power STM32L100xx block diagram
1. AF = alternate function on I/O port pin.
EXT. IT
WWDG
12-bit ADC
JTAG & SW
20 A F
JT DI
JT CK/ SWCLK
JTMS /S WDAT
NJT RST
JTDO
NRST
V
DD
=1. 8 V to 3.6 V
51 AF
AH B2
US B_DP
US B_DM
MO SI,M ISO, SCK, NS S
WKU P
F
ma x
:32MHz
V
SS
SCL, SD A, SMB us ,PM B u s
I2C 2
V
DDREF _ADC
*
GP DMA
TIM2
TIM3
XTAL OSC
1-24 MHz
XTA L32 kHz
OSC_IN
OSC_OUT
OS C32 _OUT
OS C32 _IN
PLL &
APB1 : F
ma x
=32MHz
A HBP CL K
HC L K
clock
management
AP BP CL K
as AF
as AF
VOLT. REG.
V
CORE
PO WER
as A F
TIM4
BusMatri x
Int er face
RT C
RC HS
Ibus
Db us
obl
Flash
US B RAM 512 B
US ART 1
US ART 2
SP I2
7 channels
SC L, SDA
I2C 1
as AF
RX ,TX, CT S, RT S,
US ART 3
V
SS REF_ ADC
*
AHB:F
max
=32 MHz
4Channels
4Channels
4Channels
FC LK
IWDG
@V DD
Supply
monitoring
@V DD A
VDDA /
VSS A
@V DD A
Sm artC ard a s AF
RX ,TX, CTS, RTS,
Sm ar tCar d as AF
RX ,TX, CTS, RTS,
Sm artCa rd as A F
AP B2 : F
ma x
=32 MHz
NV IC
SPI 1
MOSI ,MISO,
SC K, NS S as AF
IF
@VD D A
PV D
Power reset
Int
AHB 2
AW U
@V DD A
RTC_OUT,
RTC _TS,RTC_TAMP
Syst em
PA [ 15:0 ]
PB [ 15:0 ]
PC[ 15:0 ]
PD2
LCD 8x28 (4x32 )
SEG x
COM x
IFIFIF
@V DD A
DAC_OUT1 as
AF
MP U
Co m p 2
COMP2 _IN- /IN+
Co m p 1
TIM6
TIM7M
TIM9
TIM10
TIM11
2 Channels
1 Ch annel
1 Channel
General purpose
timers
128 KB Flash
2 KB data EEPROM
LCD step-up
converter
V
LCD
=2.5 V to 3.6 V
V
LC D
BA SI C TIM ERS
RTC_AFIN
VR EF O UTPU T
Ai15687hV3
Cortex-M3 CPU
RAM
10 KB
12-bit DAC1
12-bit DAC2
GPIOA
GPIOB
GPIOC
GPIOD
RC MS
RC LS
Standby interface
Backup interface
USB 2.0 FS device
BOR/V
REFINT
Power-up/
Power-down
Backup
register
DAC_OUT2 as
AF
AHB/APB2 AHB/APB1