Datasheet

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

February 2013 DocID024295 Rev 1 1/102

STM32L100C6 STM32L100R8

STM32L100RB

Ultralow power 32-bit MCU ARM®-based Cortex™-M3,

128KB Flash, 10KB SRAM, 2KB EEPROM, LCD, USB, ADC, DAC

Datasheet − preliminary data

Features

• Ultralow power platform

– 1.8 V to 3.6 V power supply

– -40°C to 85°C temperature range

– 0.3 µA Standby mode (3 wakeup pins)

– 0.9 µA Standby mode + RTC

– 0.57 µA Stop mode (16 wakeup lines)

– 1.2 µA Stop mode + RTC

– 9 µA Low-power Run mode

– 214 µA/MHz Run mode

– 10 nA ultra-low I/O leakage

– < 8 µs wakeup time

• Core: ARM 32-bit Cortex

™

-M3 CPU

– From 32 kHz up to 32 MHz max

– 33.3 DMIPS peak (Dhrystone 2.1)

– Memory protection unit

• Reset and supply management

– Ultrasafe, low power BOR (brownout reset)

with 5 selectable thresholds

– Ultralow power POR/PDR

– Programmable voltage detector (PVD)

• Clock sources

– 1 to 24 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– High Speed Internal 16 MHz

– Internal Low Power 37 kHz RC

– Internal multispeed low power 65 kHz to

4.2 MHz

– PLL for CPU clock and USB (48 MHz)

• Pre-programmed bootloader

– USART supported

• Development support

– Serial wire debug supported

– JTAG supported

• Up to 51 fast I/Os (42 I/Os 5V tolerant), all

mappable on 16 external interrupt vectors

• Memories

– Up to 128 KB Flash with ECC

– Up to 10 KB RAM

– Up to 2 KB of true EEPROM with ECC

– 20 Byte Backup Register

• LCD Driver for up to 8x28 segments

• Analog peripherals

– 12-bit ADC 1 Msps up to 20 channels

– 12-bit DAC 2 channels with output buffers

– Two ultralow power comparators

• Seven DMA controller channels

• Eight communication interface peripherals

– One USB 2.0

– Three USART (ISO 7816, IrDA)

– Two SPI (16 Mbits/s)

– Two I2C (SMBus/PMBus)

• Ten timers:

– Six16-bit timers with up to 4 IC/OC/PWM

channels

– Two 16-bit basic timers

– Two watchdog timers (independent and

window)

• CRC calculation unit

UFQFPN48

7 x 7 mm

LQFP64

10 x 10 mm

www.st.com

Summary of content (102 pages)

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STM32L100C6 STM32L100R8 STM32L100RB Ultralow power 32-bit MCU ARM®-based Cortex™-M3, 128KB Flash, 10KB SRAM, 2KB EEPROM, LCD, USB, ADC, DAC Datasheet − preliminary data LQFP64 10 x 10 mm • Development support – Serial wire debug supported – JTAG supported UFQFPN48 7 x 7 mm • Up to 51 fast I/Os (42 I/Os 5V tolerant), all mappable on 16 external interrupt vectors Features • Ultralow power platform – 1.8 V to 3.6 V power supply – -40°C to 85°C temperature range – 0.3 µA Standby mode (3 wakeup pins) – 0.
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Contents STM32L100C6, STM32L100R8/RB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Ultralow power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2.
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STM32L100C6, STM32L100R8/RB 3.15 Contents 3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15.
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Contents 7 STM32L100C6, STM32L100R8/RB 6.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.15 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.
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STM32L100C6, STM32L100R8/RB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. 6/102 STM32L100C6, STM32L100R8/RB USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32L100C6, STM32L100R8/RB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Ultralow power STM32L100xx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock tree . .
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Introduction 1 STM32L100C6, STM32L100R8/RB Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L100C6 and STM32L100R8/B ultralow power ARM® Cortex™-based microcontrollers product line. The ultralow power STM32L100xx(1) family includes devices in 2 different package types: 48 or 64 pins.
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STM32L100C6, STM32L100R8/RB 2 Description Description The ultralow power STM32L100xx incorporates the connectivity power of the universal serial bus (USB) with the high-performance ARM Cortex™-M3 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (Flash memory up to 128 Kbytes and RAM up to 10 Kbytes) and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
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Description 2.1 STM32L100C6, STM32L100R8/RB Device overview Table 1. Ultralow power STM32L100xx device features and peripheral counts Peripheral STM32L100C6 Flash (Kbytes) 32 Data EEPROM (Kbytes) Communication interfaces 128 8 10 4 General-purpose 6 Basic 2 SPI 2 I2C 2 USART 3 USB 1 GPIOs 12-bit synchronized ADC Number of channels 37 51 1 16 channels 1 20 channels 12-bit DAC Number of channels 2 2 LCD COM x SEG 4x32 8x28 4x16 Comparator 2 Max.
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STM32L100C6, STM32L100R8/RB 2.2 Description Ultralow power device continuum The ultralow power STM32L100C6 and STM32L100R8/B are fully pin-to-pin and software compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers ultralow power strategy which also includes STM8L1xx and STM8L0xx devices. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture and features.
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Functional overview 3 STM32L100C6, STM32L100R8/RB Functional overview Figure 1 shows the block diagrams. Figure 1. Ultralow power STM32L100xx block diagram @V DD J TAG & SW Flash obl Int erface Cortex-M3 CPU Ibus F ma x : 32 M Hz MP U Db u s Syst em NV IC GP DMA A HBP CL K AP BP CL K HC L K FC LK @V DD A Supply monitoring BOR/VREFINT VDDA / VSS A RC MS GPIOB PC[15:0 ] GPIOC PD2 AH B2 MOSI ,MISO, SC K, NS S as AF SPI 1 AHB 2 AHB/APB1 APB1 : F ma x =32MHz EXT.
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STM32L100C6, STM32L100R8/RB 3.1 Functional overview Low power modes The ultralow power STM32L100xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply: • In range 1 (VDD range limited to 2.0-3.6 V), the CPU runs at up to 32 MHz (refer to Table 15 for consumption).
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Functional overview STM32L100C6, STM32L100R8/RB HSE crystal oscillators are disabled. The voltage regulator is in the low power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB wakeup.
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STM32L100C6, STM32L100R8/RB Functional overview Table 3. CPU frequency range depending on dynamic voltage scaling CPU frequency range Dynamic voltage scaling range 16 MHz to 32 MHz (1ws) 32 kHz to 16 MHz (0ws) Range 1 8 MHz to 16 MHz (1ws) 32 kHz to 8 MHz (0ws) Range 2 2.1 MHz to 4.2 MHz (1ws) 32 kHz to 2.
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Functional overview STM32L100C6, STM32L100R8/RB Table 4.
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STM32L100C6, STM32L100R8/RB Functional overview Table 4. Working mode-dependent functionalities (from Run/active down to standby) (continued) Run/Active Sleep DAC Y Y Y Y Y Comparators Y Y Y Y Y 16-bit and 32-bit Timers Y Y Y Y -- IWDG Y Y Y Y Y WWDG Y Y Y Y -- Systic Timer Y Y Y Y GPIOs Y Y Y Y 0 µs 0.
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Functional overview STM32L100C6, STM32L100R8/RB Nested vectored interrupt controller (NVIC) The ultralow power STM32L100xx embeds a nested vectored interrupt controller able to handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.
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STM32L100C6, STM32L100R8/RB Functional overview Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit.
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Functional overview 3.4 STM32L100C6, STM32L100R8/RB Clock management The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.
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STM32L100C6, STM32L100R8/RB Functional overview Figure 2. Clock tree -3) 2# -3) !$##,+ TO !$# 0ERIPHERAL CLOCK ENABLE -(Z (3) 2# (3) -(Z 53"#,+ TO 53" INTERFACE 0,,6#/ 0,,32# /3#?/54 /3#?).
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Functional overview 3.5 STM32L100C6, STM32L100R8/RB Low power real-time clock and backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes.
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STM32L100C6, STM32L100R8/RB 3.7 Functional overview Memories The STM32L100xx devices have the following features: • Up to 10 Kbyte of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses).
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Functional overview 3.10 STM32L100C6, STM32L100R8/RB ADC (analog-to-digital converter) A 12-bit analog-to-digital converters is embedded into STM32L100xx devices with up to 20 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels.
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STM32L100C6, STM32L100R8/RB Functional overview Eight DAC trigger inputs are used in the STM32L100xx. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.12 Ultralow power comparators and reference voltage The STM32L100xx embeds two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O).
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Functional overview 3.14.1 STM32L100C6, STM32L100R8/RB General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) There are six synchronizable general-purpose timers embedded in the STM32L100xx devices (see Table 6 for differences). TIM2, TIM3, TIM4 These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output.
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STM32L100C6, STM32L100R8/RB 3.14.5 Functional overview Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.15 Communication interfaces 3.15.1 I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes.
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Functional overview 3.16 STM32L100C6, STM32L100R8/RB CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity.
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STM32L100C6, STM32L100R8/RB Pin descriptions VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 3.
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Pin descriptions STM32L100C6, STM32L100R8/RB 0! 6$$? 0# 7+50 633? 0# /3# ?). 0! 0# /3# ?/54 0! 0( /3#?). 0! 0( /3#?/54 0! .234 0! 633! 0! 6$$! 0" 0! 7+50 0" 0! 0" 0! 0" 0" 5&1&0.
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STM32L100C6, STM32L100R8/RB Pin descriptions Table 7.
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Pin descriptions STM32L100C6, STM32L100R8/RB Table 7.
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STM32L100C6, STM32L100R8/RB Pin descriptions Table 7.
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Pin descriptions STM32L100C6, STM32L100R8/RB 4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is on (by setting the LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose PC14/PC15 I/Os, respectively, when the LSE oscillator is off ( after reset, the LSE oscillator is off ). The LSE has priority over the GPIO function.
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Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15 Alternate function SYSTEM BOOT0 BOOT0 NRST NRST TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART 1/2/3 DocID024295 Rev 1 PA0-WKUP1 WKUP1 TIM2_CH1_ ETR USART2_ CTS PA1 TIM2_CH2 USART2_ RTS PA2 TIM2_CH3 TIM9_CH1 PA3 TIM2_CH4 TIM9_CH2 PA4 SPI1_NSS TIM2_CH1_ ETR PA5 N/A N/A USB LCD TIM3_CH1 TIM10_CH1 SPI1_MISO PA7 TIM3_CH2 TIM11_
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Digital alternate function number Port name AFIO0 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15 Alternate function SYSTEM PA15 AFIO1 JTDI TIM2 PB1 DocID024295 Rev 1 BOOT1 PB3 JTDO PB4 JTRST TIM9/10/11 I2C1/2 TIM2_CH1_ ETR PB0 PB2 TIM3/4 SPI1/2 N/A USART 1/2/3 SPI1_NSS N/A N/A USB LCD SEG17 N/A N/A RI TIMx_IC4 SYSTEM EVENTOUT TIM3_CH3 [SEG5] EVENTOUT TIM3_CH4 [SEG6] EVENTOUT EVENTOUT TIM2_CH2 TIM3_CH1 SPI1_SCK [SEG7]
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Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15 Alternate function SYSTEM TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART 1/2/3 N/A N/A USB LCD N/A N/A RI SYSTEM PC2 SEG20 TIMx_IC3 EVENTOUT PC3 SEG21 TIMx_IC4 EVENTOUT PC4 SEG22 TIMx_IC1 EVENTOUT PC5 SEG23 TIMx_IC2 EVENTOUT DocID024295 Rev 1 PC6 TIM3_CH1 SEG24 TIMx_IC3 EVENTOUT PC7 TIM3_CH2 SEG25 TIMx_IC4 EVENTOUT
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Digital alternate function number Port name AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15 Alternate function SYSTEM TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART 1/2/3 N/A N/A USB LCD N/A N/A RI Pin descriptions 38/102 Table 8.
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STM32L100C6, STM32L100R8/RB 5 Memory mapping Memory mapping The memory map is shown in the following figure.
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Memory mapping STM32L100C6, STM32L100R8/RB Figure 5.
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STM32L100C6, STM32L100R8/RB Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 6.1.6 STM32L100C6, STM32L100R8/RB Power supply scheme Figure 8. Power supply scheme /54 '0 ) /S ). ,EVEL SHIFTER 3TANDBY POWER CIRCUITRY /3# + 24# 7AKE UP LOGIC 24# BACKUP REGISTERS )/ ,OGIC +ERNEL LOGIC #05 $IGITAL -EMORIES 6$$ 6$$ . 2EGULATOR . X N& X & 633 . 6$$ 6$$! N& & !$# !NALOG 2#S 0,, 633! -3 6 6.1.7 Current consumption measurement Figure 9.
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STM32L100C6, STM32L100R8/RB 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 9: Voltage characteristics, Table 10: Current characteristics, and Table 11: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 9.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Table 11. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 6.3 Operating conditions 6.3.1 General operating conditions Value Unit –65 to +150 °C 105 °C Table 12.
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STM32L100C6, STM32L100R8/RB 6.3.2 Electrical characteristics Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in the following table. Table 13.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Table 13. Embedded reset and power control block characteristics (continued) Symbol Parameter Vhyst Conditions Hysteresis voltage Min Typ BOR0 threshold 40 All BOR and PVD thresholds excepting BOR0 100 Max Unit mV 1. Guaranteed by characterization, not tested in production. 6.3.3 Embedded internal reference voltage The parameters given in the following table are based on characterization results, unless otherwise specified. Table 14.
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STM32L100C6, STM32L100R8/RB Electrical characteristics 1. Tested in production. 2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes. 3. Guaranteed by design, not tested in production. 4. Shortest sampling time can be determined in the application by multiple iterations. 5. To guarantee less than 1% VREF_OUT deviation.
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Electrical characteristics 6.3.4 STM32L100C6, STM32L100R8/RB Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 9: Current consumption measurement scheme.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Table 16. Current consumption in Run mode, code with data processing running from RAM Symbol Parameter Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 fHSE = fHCLK up to 8 MHz, Range 2, included VCORE=1.5 V fHSE = fHCLK/2 above VOS[1:0] = 10 8 MHz (2) (PLL ON) Range 1, Supply current in VCORE=1.8 V Run mode, code IDD (Run VOS[1:0] = 01 executed from from RAM) RAM, Flash Range 2, switched off VCORE=1.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Table 17. Current consumption in Sleep mode Symbol Parameter Conditions Supply current in Sleep mode, code executed from RAM, Flash switched HSI clock source (16 OFF MHz) MSI clock, 524 kHz (Sleep) 80 140 140 2 MHz 150 210 210 4 MHz 280 330 330 4 MHz 280 400 400 8 MHz 450 550 550 16 MHz 900 1050 1050 8 MHz 550 650 650 16 MHz 1050 1200 1200 32 MHz 2300 2500 2500 Range 2, VCORE=1.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Table 18. Current consumption in Low power run mode Symbol IDD (LP Run) IDD Max (LP Run)(2) Parameter Supply current in Low power run mode Conditions All peripherals OFF, code executed from RAM, Flash switched OFF, VDD from 1.8 V to 3.6 V All peripherals OFF, code executed from Flash, VDD from 1.8 V to 3.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Table 19. Current consumption in Low power sleep mode Symbol Parameter Conditions MSI clock, 65 kHz fHCLK = 32 kHz Flash OFF IDD (LP Sleep) Supply current in Low power sleep mode MSI clock, 65 kHz fHCLK = 32 kHz All peripherals Flash ON OFF, VDD MSI clock, 65 kHz from 1.8 V fHCLK = 65 kHz, to 3.6 V Flash ON Typ TA = -40 °C to 25 °C TIM9 and USART1 enabled, Flash ON, VDD from 1.8 V to 3.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Table 20. Typical and maximum current consumptions in Stop mode Symbol Parameter RTC clocked by LSI, regulator in LP mode, HSI and HSE OFF (no independent watchdog) Supply current in Stop mode with with RTC) RTC enabled Max Typ(1) (1)(2) Unit Conditions TA = -40°C to 25°C VDD = 1.8 V 1.2 2.75 LCD OFF TA = -40°C to 25°C 1.4 4 TA = 55°C 2.6 6 TA= 85°C 4.8 10 T = -40°C to 25°C LCD ON A (static TA = 55°C duty)(3) TA= 85°C 3.3 6 4.
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Electrical characteristics STM32L100C6, STM32L100R8/RB 1. The typical values are given for VDD = 3.0 V and max values are given for VDD = 3.6 V, unless otherwise specified. 2. Based on characterization, not tested in production, unless otherwise specified 3. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected 4. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 5.
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STM32L100C6, STM32L100R8/RB Electrical characteristics All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12. Table 22. Typical and maximum timings in Low power modes Symbol Parameter tWUSLEEP Wakeup from Sleep mode tWUSLEEP_LP Wakeup from Low power sleep mode fHCLK = 262 kHz tWUSTDBY Typ Max(1) Unit fHCLK = 32 MHz 0.36 fHCLK = 262 kHz Flash enabled 32 fHCLK = 262 kHz Flash switched OFF 34 fHCLK = fMSI = 4.2 MHz 8.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Table 23. Peripheral current consumption(1) Typical consumption, VDD = 3.0 V, TA = 25 °C Range 1, VCORE= 1.8 V VOS[1:0] = 01 Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 Low power sleep and run TIM2 13 10.5 8 10.5 TIM3 14 12 9 12 TIM4 12.5 10.5 8 11 TIM6 5.5 4.5 3.5 4.5 TIM7 5.5 5 3.5 4.5 LCD 5.5 5 3.5 5 4 3.5 2.5 3.5 5.5 5 4 5 USART2 9 8 5.5 8.5 USART3 10.5 9 6 8 I2C1 8.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Table 23. Peripheral current consumption(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 °C Range 1, VCORE= 1.8 V VOS[1:0] = 01 Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 Low power sleep and run SYSCFG & RI 3 2.5 2 2.5 TIM9 9 7.5 6 7 TIM10 6.5 5.5 4.5 5.5 TIM11 7 6 4.5 5.5 11.5 9.5 8 9 SPI1 5 4.5 3 4 USART1 9 7.5 6 7.5 GPIOA 5 4.5 3.5 4 GPIOB 5 4.5 3.5 4.
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Electrical characteristics STM32L100C6, STM32L100R8/RB 4. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD/2. DAC is in buffered mode, output is left floating. 5. Including supply current of internal reference voltage. 6.3.5 External clock source characteristics High-speed external user clock generated from an external source Table 24.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 12. Table 25. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit 1 32.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Figure 11. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR (3% TF (3% T7 (3% /3# ?). ), T7 (3% T 4(3% %84%2 .!, #,/#+ 3/52# % F(3%?EXT 34- ,XX AI High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Table 26. HSE 1-24 MHz oscillator characteristics(1)(2) Symbol Parameter Conditions fOSC_IN Oscillator frequency 1 RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) IHSE IDD(HSE) gm tSU(HSE) (4) HSE driving current HSE oscillator power consumption Oscillator transconductance Startup time Min Typ RS = 30 Ω Max Unit 24 MHz 200 kΩ 20 pF VDD= 3.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Figure 12. HSE oscillator circuit diagram F(3% TO CORE 2M ,M 2& #/ #, /3#?). #M GM 2ESONATOR #ONSUMPTION CONTROL 2ESONATOR 34- /3#?/54 #, AI 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 13). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.
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Electrical characteristics 6.3.6 STM32L100C6, STM32L100R8/RB Internal clock source characteristics The parameters given in the following table are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12. High-speed internal (HSI) RC oscillator Table 28. HSI oscillator characteristics Symbol fHSI TRIM (1)(2) Parameter Conditions Min Frequency VDD = 3.0 V HSI user-trimmed resolution Trimming code is not a multiple of 16 Max Unit 16 ± 0.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Multi-speed internal (MSI) RC oscillator Table 30. MSI oscillator characteristics Symbol Parameter Frequency after factory calibration, done at VDD= 3.3 V and TA = 25 °C fMSI Condition Typ MSI range 0 65.5 MSI range 1 131 MSI range 2 262 MSI range 3 524 MSI range 4 1.05 MSI range 5 2.1 MSI range 6 4.2 Max Unit kHz MHz Frequency error after factory calibration ±0.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Table 30. MSI oscillator characteristics (continued) Symbol tSTAB(MSI)(2) fOVER(MSI) Parameter Condition MSI oscillator stabilization time MSI oscillator frequency overshoot Typ Max MSI range 0 40 MSI range 1 20 MSI range 2 10 MSI range 3 4 MSI range 4 2.5 MSI range 5 2 MSI range 6, Voltage range 1 and 2 2 MSI range 3, Voltage range 3 3 Any range to range 5 4 Any range to range 6 6 Unit µs MHz 1.
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STM32L100C6, STM32L100R8/RB 6.3.8 Electrical characteristics Memory characteristics The characteristics are given at TA = -40 to 85 °C unless otherwise specified. RAM memory Table 32. RAM and hardware registers Symbol VRM Parameter Conditions Data retention mode(1) STOP mode (or RESET) Min Typ Max 1.8 Unit V 1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode). Flash memory and data EEPROM Table 33.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Table 34. Flash memory, data EEPROM endurance and data retention Value Symbol NCYC(2) tRET(2) Parameter Cycling (erase / write ) Program memory Cycling (erase / write ) EEPROM data memory Data retention (program memory) after 1 kcycle at TA = 85 °C Data retention (EEPROM data memory) after 100 kcycles at TA = 85 °C Conditions TA = -40°C to 85 °C Min(1) Typ Max Unit 1 kcycles 100 10 TRET = +85 °C years 10 1.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
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Electrical characteristics 6.3.10 STM32L100C6, STM32L100R8/RB Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.
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Electrical characteristics 6.3.12 STM32L100C6, STM32L100R8/RB I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under conditions summarized in Table 12. All I/Os are CMOS and TTL compliant. Table 40. I/O static characteristics Symbol VIL VIH VIL VIH Vhys Ilkg Parameter Input low level voltage Standard I/O input high level voltage FT (2) I/O input high level voltage Conditions TTL ports 2.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with the non-standard VOL/VOH specifications given in Table 41. in the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 14 and Table 42, respectively. Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12. Table 42.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Figure 14. I/O AC characteristics definition %XTERNAL /UTPUT ON P& TR ) / OUT TF ) / OUT 4 -AXIMUM FREQUENCY IS ACHIEVED IF T R TF a 4 AND IF THE DUTY CYCLE IS WHEN LOADED BY P& AI B 6.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Figure 15. Recommended NRST pin protection 6$$ %XTERNAL RESET CIRCUIT .234 205 )NTERNAL RESET &ILTER & 34- ,XX AI 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 43. Otherwise the reset will not be taken into account by the device. 6.3.
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STM32L100C6, STM32L100R8/RB 6.3.15 Electrical characteristics Communication interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 12. The STM32L100C6 product line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: SDA and SCL are not “true” opendrain I/O pins.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Figure 16. I2C bus AC waveforms and measurement circuit 6$$ 6$$ K½ K½ ½ 34- ,XX 3$! ) # BUS ½ 3#, 3 4!24 2%0%!4%$ 3 4!24 3 4!24 TSU 34! 3$! TF 3$! TR 3$! TH 34! TSU 3$! TW 3#+, 3#, TW 3#+( TR 3#+ TH 3$! TF 3#+ TSU 34! 34/ 3 4/0 TSU 34/ AI 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 46. SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.
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STM32L100C6, STM32L100R8/RB Electrical characteristics SPI characteristics Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 12. Refer to Section 6.3.11: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 47.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Figure 17. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) tSU(NSS) SCK Input CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 18.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Figure 19. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTPUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (full speed).
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Electrical characteristics STM32L100C6, STM32L100R8/RB Table 49. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0 3.6 V V Input levels VDD VDI (3) USB operating voltage(2) Differential input sensitivity I(USB_DP, USB_DM) 0.2 VCM(3) Differential common mode range Includes VDI range 0.8 2.5 VSE(3) Single ended receiver threshold 1.3 2.0 Output levels VOL(4) Static output level low RL of 1.5 kΩ to 3.
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STM32L100C6, STM32L100R8/RB 6.3.16 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 52 are guaranteed by design. Table 51. ADC clock frequency Symbol Parameter fADC ADC clock frequency Conditions Voltage range 1 & 2 Min 2.4 V ≤VDDA ≤3.6 V Max Unit 16 1.8 V ≤VDDA ≤2.4 V 0.480 Voltage range 3 8 MHz 4 Table 52. ADC characteristics Symbol VDDA Parameter Conditions Power supply Typ 1.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Table 52.
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STM32L100C6, STM32L100R8/RB Electrical characteristics 2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Figure 23. Maximum dynamic current consumption on VDDA supply pin during ADC conversion Sampling (n cycles) Conversion (12 cycles) ADC clock IDDA 1700 µA 1300 µA Table 54. RAIN max for fADC = 16 MHz(1) RAIN max (kohm) Ts (cycles) Ts (µs) Multiplexed channels Direct channels 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V 4 0.25 Not allowed Not allowed 0.7 Not allowed 9 0.5625 0.8 Not allowed 2.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Figure 24.
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Electrical characteristics 6.3.17 STM32L100C6, STM32L100R8/RB DAC electrical specifications Data guaranteed by design, not tested in production, unless otherwise specified. Table 55. DAC characteristics Symbol Parameter VDDA Analog supply voltage IDDA(1) Current consumption on VDDA supply VDDA = 3.3 V RL(2) Resistive load CL(2) Capacitive load RO Output impedance VDAC_OUT DNL(1) INL(1) Offset Offset1(1) dOffset/dT(1) 88/102 Min Typ 1.8 Max Unit 3.
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STM32L100C6, STM32L100R8/RB Electrical characteristics Table 55. DAC characteristics (continued) Symbol Gain(1) dGain/dT(1) TUE(1) tSETTLING Parameter (7) Gain error Gain error temperature coefficient Total unadjusted error Conditions Min CL ≤ 50 pF, RL ≥ 5 kΩ DAC output buffer ON Typ Max Unit +0.1 / -0.2% +0.2 / -0.5% % No RLOAD, CL ≤ 50 pF DAC output buffer OFF VDDA = 3.3V TA = 0 to 50 ° C DAC output buffer OFF -10 VDDA = 3.3V TA = 0 to 50 ° C DAC output buffer ON -40 +0 / -0.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Figure 25. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DAC_OUTx C LOAD ai17157V2 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.
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STM32L100C6, STM32L100R8/RB 6.3.18 Electrical characteristics Comparator Table 56. Comparator 1 Symbol Parameter Conditions Min(1) Typ VDDA Analog supply voltage R400K R400K value 400 R10K R10K value 10 VIN tSTART Comparator 1 input voltage range Propagation delay Voffset Comparator offset ICOMP1 0.6 Comparator startup time td dVoffset/dt 1.8 (2) Comparator offset variation in worst voltage stress conditions VDDA = 3.
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Electrical characteristics STM32L100C6, STM32L100R8/RB Table 57. Comparator 2 characteristics Symbol VDDA VIN Parameter Min Analog supply voltage 1.8 Comparator 2 input voltage range 0 tSTART Comparator startup time td slow Propagation delay(2) in slow mode td fast Propagation delay(2) in fast mode Voffset Comparator offset error dThreshold/ Threshold voltage temperature dt coefficient ICOMP2 Conditions Current consumption(3) Typ Max(1) Unit 3.
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STM32L100C6, STM32L100R8/RB 6.3.19 Electrical characteristics LCD controller The STM32L100xx embeds a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 58. LCD controller characteristics Symbol Parameter Min Typ VLCD LCD external voltage VLCD0 LCD internal reference voltage 0 2.6 VLCD1 LCD internal reference voltage 1 2.
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Package characteristics STM32L100C6, STM32L100R8/RB 7 Package characteristics 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 26. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline ! C ! ! 3%!4).' 0,!.
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STM32L100C6, STM32L100R8/RB Package characteristics Table 59. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max A Min Typ 1.600 A1 0.050 0.150 Max 0.0630 0.0020 0.0059 A2 1.400 1.350 1.450 0.0551 0.0531 0.0571 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 0.090 0.200 0.0035 0.0079 c D 12.000 11.800 12.200 0.4724 0.4646 0.4803 D1 10.000 9.800 10.200 0.3937 0.3858 0.4016 D3 7.500 E 12.000 11.800 12.
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Package characteristics STM32L100C6, STM32L100R8/RB Figure 28. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline 0IN INDENTIFIER LASER MARKING AREA $ ! % % 4 DDD ! 3EATING PLANE B E $ETAIL 9 $ %XPOSED PAD AREA 9 $ , # X PIN CORNER % 2 TYP $ETAIL : : ! " ?-%?6 1. Drawing is not to scale. 1. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 1. There is an exposed die pad on the underside of the UFQFPN package.
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STM32L100C6, STM32L100R8/RB Package characteristics Table 60. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T b 0.152 0.200 0.0060 0.250 e 0.300 0.0079 0.0098 0.500 0.0118 0.0197 1.
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Package characteristics 7.2 STM32L100C6, STM32L100R8/RB Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
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STM32L100C6, STM32L100R8/RB 7.2.1 Package characteristics Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.
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Ordering information scheme 8 STM32L100C6, STM32L100R8/RB Ordering information scheme Table 62.
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STM32L100C6, STM32L100R8/RB 9 Revision history Revision history on Table 63. Document revision history Date Revision 21-Feb-2013 1 Changes Initial release.
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STM32L100C6, STM32L100R8/RB Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.