Datasheet

DocID022152 Rev 4 27/185
STM32F405xx, STM32F407xx Description
The following conditions must be respected:
• V
DD
should always be higher than V
CAP_1
and V
CAP_2
to avoid current injection
between power domains.
• If the time for V
CAP_1
and V
CAP_2
to reach V
12
minimum value is faster than the time for
V
DD
to reach 1.8 V, then PA0 should be kept low to cover both conditions: until V
CAP_1
and V
CAP_2
reach V
12
minimum value and until V
DD
reaches 1.8 V (see Figure 10).
• Otherwise, if the time for V
CAP_1
and V
CAP_2
to reach V
12
minimum value is slower
than the time for V
DD
to reach 1.8 V, then PA0 could be asserted low externally (see
Figure 11).
• If V
CAP_1
and V
CAP_2
go below V
12
minimum value and V
DD
is higher than 1.8 V, then
a reset must be asserted on PA0 pin.
Note: The minimum value of V
12
depends on the maximum frequency targeted in the application
(see Table 14: General operating conditions).
Figure 10. Startup in regulator OFF mode: slow V
DD
slope
- power-down reset risen after V
CAP_1
/V
CAP_2
stabilization
1. This figure is valid both whatever the internal reset mode (onON or OFFoff).
2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges.
ai18491e
V
DD
time
Min V
12
PDR = 1.7 V or 1.8 V
(2)
V
CAP_1
/V
CAP_2
V
12
NRST
time