Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
138/185 DocID022152 Rev 4
Asynchronous waveforms and timings
Figure 55 through Figure 58 represent asynchronous waveforms and Table 75 through
Table 78 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
• AddressSetupTime = 1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1
• BusTurnAroundDuration = 0x0
In all timing tables, the
T
HCLK
is the HCLK clock period.
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 2T
HCLK
–0.5 2 T
HCLK
+1 ns
t
v(NOE_NE)
FSMC_NEx low to FSMC_NOE low 0.5 3 ns
t
w(NOE)
FSMC_NOE low time 2T
HCLK
–2 2T
HCLK
+ 2 ns
t
h(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time 0 - ns
t
v(A_NE)
FSMC_NEx low to FSMC_A valid - 4.5 ns
t
h(A_NOE)
Address hold time after FSMC_NOE high 4 - ns
Data
FSMC_NE
FSMC_NBL[1:0]
FSMC_D[15:0]
t
v(BL_NE)
t
h(Data_NE)
FSMC_NOE
Address
FSMC_A[25:0]
t
v(A_NE)
FSMC_NWE
t
su(Data_NE)
t
w(NE)
ai14991c
w(NOE)
tt
v(NOE_NE)
t
h(NE_NOE)
t
h(Data_NOE)
t
h(A_NOE)
t
h(BL_NOE)
t
su(Data_NOE)
FSMC_NADV
(1)
t
v(NADV_NE)
t
w(NADV)